This paper describes a high-speed and low-complexity implementation of FIR filter using least mean square technique. The proposed structure of multiplexed based zero-adaptation-delay structure and two adaptation delay structure for a direct LMS adaptive FIR filter. This paper describes the proposed adder technique provides much faster convergence and lower complexity for obtaining lower area, power dissipation, high speed and lower propagation delay. The multiplexer circuits were schematized using the DSCH2 schematic design tool, and their layouts were generated with the Micro wind 2 VLSI layout CAD tool. The parameter analyses were performed with a BSIM4 analyzer. The proposed multiplex -based filters are use carry save adder as well as other existing adder circuit in terms of power dissipation, propagation delay, latency, and throughput. Our proposed structure involves the minimum power. Finally the simulations are done using Xilinx ISE design suite to get power and implemented on Spartan 3E FPGA kit.