In this paper, Wallace tree multiplier using the constant delay logic style and less number of transistors were designed and analyzed. Constant Delay (CD) logic provides low power consumption and to adjust the window width of the clock pulse, CD logic produces quick output evaluation before the input arrival for operation. Using these features, performance is good compared to normal static and dynamic logic. In this design, the timing block and logic block are implemented to reduce the static power dissipation and also to reduce the unwanted glitch in the output. This experimental result shows smaller power consumption and reduced chip area compared to the existing design.