The high speed dual modulus prescaler is one of the important functional blocks in frequency synthesizers. The dual modulus prescaler design is the bottleneck of the synthesizer, as it operates at the highest frequencies and consumes more power than any other circuit blocks of the synthesizer. A dual modulus prescaler (also known as divide-by-N/N+1 counter) normally consists of a divide-by-2/3 prescaler unit followed by several asynchronous divide-by-2 units. Usually, dual modulus prescaler consists of Flip flops and some extra logic implemented using logic gates which determine the terminal count. Here an E-TSPC [Extended True Single Phase Clock] logic based divide-by-2/3 prescaler using pass transistor logic is suitable for low supply voltage (0.9V) and low power applications have been designed and implemented. Here the counting logic and the mode selection control are implemented using a single P-MOS transistor. Thus the critical path is reduced and also increases its working frequency. Simulation results show that, compared with the conventional TSPC [True Single Phase Clock] and E-TSPC based 2/3 prescaler designs as much as 46% in PDP, 24% in operation speed and 44% in area can be achieved by the proposed design. Also the proposed 2/3 prescaler are designed and implemented to design a 32/33 prescaler, 47/48 prescaler and a multimodulus 32/33/47/48 prescaler. The power dissipation of the proposed multimodulus prescaler is lesser than the existing multimodulus prescaler designs shown by the simulation results.