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Low Power dissipation of Ring Counter using Dual sleep Transistor approach

M. Balaji*, B. Keerthana**, K. Varun***

* Asstistant Professor, Department of EIE, Sree Vidyanikethan Engineering College, Tirupati, India

**-*** Student, Department of EIE, Sree Vidyanikethan Engineering College, Tirupati, India

Periodicity:March - May'2014
DOI : https://doi.org/10.26634/jele.4.3.2674

Abstract

In CMOS [Complementary Metal Oxide Semiconductor] integrated circuits design, scaling is challenged by higher power consumption. The significant growth in power dissipation has occurred mainly due to the higher clock speeds in addition to the smaller process geometries. The transistor packaging density and functionality on a chip is improved by scaling. The speed and frequency of operation is increased due to scaling and hence higher performance is achieved. When the technology scales down, then the leakage current increases exponentially. In 90 nm and below technologies, leakage power constitutes 30-40% of total power dissipation. In this paper, a dual sleep transistor approach is used for reducing the power dissipation of ring counter circuit with minimum possible area. The simulations were done using Micro wind Layout Editor and DSCH [Digital Schematic Editor] software.

Keywords

CMOS [Complementary Metal Oxide Semiconductor], Scaling, Leakage Power, Power Dissipation, D Flip-flop, Ring Counter, Conventional Logic Gates, Schema Symbol, Dual Sleep Transistor Approach, Analog Simulation.

How to Cite this Article?

Balaji, M., Keerthana, B., and Varun, K. (2014). Low Power Dissipation Of Ring Counter Using Dual Sleep Transistor Approach. i-manager's Journal on Electronics Engineering, 4(3), 9-13. https://doi.org/10.26634/jele.4.3.2674

References

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Low Power dissipation of Ring Counter using Dual sleep Transistor approach

Abstract

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