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Analysis and Design of Hysteresis Comparator

M. Bharanidharan*, M. Shenbagapriya**, N. Santhiyakumari***

* M.E Student, Knowledge Institute of Technology, Salem, India.

** Assistant Professor, Department of Electronics and Communication Engineering, Knowledge Institute of Technology, Salem, India.

*** Professor and Head, Department of Electronics and Communication Engineering, Knowledge Institute of Technology, Salem, India.

Periodicity:November - January'2014
DOI : https://doi.org/10.26634/jcs.3.1.2633

Abstract

The main building block of any portable electronic equipment is the Analog-to-Digital Converter. The increased demand of the portable electronic equipments has forced the circuit designers to use lower supply voltages. However, the performance of analog circuits is degraded at low supply voltage due to large power dissipation and higher noise occurrence. This makes the design of voltage analogue circuits more challenging. As comparator is the basic device of analog to digital converters, this paper aims to analyze the comparator design with hysteresis. This proposed technique reduces the power dissipation and noise. The results were compared with the double tail comparator, which operates with supply voltage of 0.6v.

Keywords

How to Cite this Article?

Bharanidharan, M., Shenbagapriya, M., and Santhiyakumari, N. (2014). Analysis and Design of Hysteresis Comparator. i-manager’s Journal on Communication Engineering and Systems, 3(1), 16-21. https://doi.org/10.26634/jcs.3.1.2633

References

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