The design of high speed Content addressable memory (CAM) offers high speed search function in a single clock cycle. Content addressable memory is a memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. In the CAM design techniques at the circuit level and at the architectural level. At the circuit level, low-power match-line sensing techniques and search line driving approaches are utilized. In the existing system, introduce a parity bit that leads to sensing delay reduction at a cost of less than area and power overhead. Thus robust, high-speed and low-power match line sense amplifiers are highly sought after in CAM designs. In the proposed system, introduce a double parity bit for searching data, speed and power is increased. Without sacrificing speed, power is reduced by using gated clock technique.