Performance Analysis of Three Level Diode Clamped Inverter with Two Level Voltage Source Inverter

E. Chandra Sekaran*, P. Anbalagan**, S. Elango***
* Selection Grade Lecturer, Department of EEE, Coimbatore Institute of Technology, Coimbatore.
** Principal, KIT, Kannampalayam, Coimbatore.
*** Power House Engineer, Department of EEE, Coimbatore Institute of Technology, Coimbatore.
Periodicity:January - March'2009
DOI : https://doi.org/10.26634/jee.2.3.255

Abstract

The usage of non-linear loads like variable speed drives, SMPS, UPS, etc., connected to power systems cause the harmonic currents which make sinusoidal currents/voltages to non-sinusoidal currents/voltages. Harmonic voltage results from the harmonic currents interacting with the impedance of the power systems, which results in the power quality problem. In this research paper, the harmonic levels of a sinusoidal pulse width modulated two level three-phase inverter are compared with the sinusoidal pulse width modulated three level inverter. The three-phase three level diode clamp inverter is designed and simulated using PSpice and the DSP based hardware model is developed using IGBT as the power devices. The hardware model is tested for resistive load, which results are obtained with the help of Fluke 434 power quality analyzer. In this multilevel inverter the magnitude of the fundamental component is increased and the total harmonic distortion decreased by 50% for both practical and simulated cases, when compared to the three phase two level conventional PWM inverter.

Keywords

Harmonics, THD, Diode Clamped Multi level Inverter

How to Cite this Article?

E. Chandra Sekaran, P. Anbalagan and S. Elango (2009). Performance Analysis Of Three Level Diode Clamped Inverter With Two Level Voltage Source Inverter. i-manager’s Journal on Electrical Engineering, 2(3), Jan-Mar 2009, Print ISSN 0973-8835, E-ISSN 2230-7176, pp. 26-35. https://doi.org/10.26634/jee.2.3.255

References

[1]. Baker R.H. (1975), “Electric Power Converter”, U.S. Patent Number 3,867,643.
[2]. Nabae A., Takahashi I. and Akagi H. (1981), “A new neutral-point-clamped PWM inverter”, IEEE Transactions on Industry Applications, Vol. 17, No. 5, pp. 518-523 .
[3]. Bhagwat P. and Stefanovic V. (1983), “Generalized Structure of a Multilevel PWM Inverter”, IEEE Transactions on Industry Applications, Vol. 19, No. 6, pp. 1057-1069.
[4]. Brumsickle W., Divan D. and Lipo T. (1998), “Reduced Switching Stress in High-Voltage IGBT Inverters via a Three- Level Structure”, IEEE-Applied Power Electronics Conference and Exposition, Vol. 2, pp. 544-550.
[5]. Stemmler K. and Guggenbach P. (1993), '”Configurations of High-Power Voltage Source Inverter Drives”, Proceedings of the European Conference on Power Electronics and Applications, Vol. 5, pp. 7-14.
[6]. Kawabatta T., Kawabata Y. and Nishiyama K. (1996) , '”New Configuration of High-Power Inverter Drives”, Proceedings of the IEEE International Symposium on Industrial Electronics,Vol.2, pp. 850-855.
[7]. Strzelecki R., Benysek G., Rusiski J. and Kot E. (2001), '”Analysis of DC Link Capacitor Voltage Balance in Multilevel Active Power Filter”', EPE Conference, pp. P.1-P.8.
[8]. Grzegorz Benysek (2007),”Improvement in the Quality of Delivery of Electrical Energy using Power Electronics Systems”, Springer-Verlag, London Limited.
[9]. Muhammad H. Rashid (2004), “Power Electronics Handbook”, Elsevier Publishers.
[10]. Peng F.Z. and Lai J.S. (1997), “Dynamic Performance and Control of a Static Var Generator Using Cascade Multilevel Inverter ”, IEEE Transaction on Industry Applications, Vol. 33, No. 2, pp. 748-755.
[11]. Jih-Sheng Lai and Fang Zheng Peng (1996), “Multilevel Converters - A New Breed of Power Converters”, IEEE Transactions on Industry Applications, Vol. 32, No. 3, pp. 509-517.
[12]. Fang Zheng Peng (2001), “A Generalized Multilevel Inverter Topology with Self Voltage Balancing”, IEEE Transactions on Industry Applications, Vol. 37, No. 2, pp. 611-618.
[13]. Fracchia M., Ghiara T., Marchesoni M. and Mazzucchelli M. (1992), “Optimized Modulation Techniques for the Generalized N-Level Converter”, Proceedings of the IEEE Power Electronics Specialist Conference, Vol. 2, pp. 1205-1213.
[14]. Yamanaka K., Yamada A., Kumagae A. and Terada T. (2001), “Three-Level Neutral Point Clamping Type Inverter Circuit”, U.S. Patent Number 06,226,192, Assigned to Kabushiki Kaisha Yaskawa Denki.
[15]. Nikola Celanovic and Dushan Boroyevich (2000), “A Comprehensive Study of Neutral - Point Voltage Balancing Problem in Three-Level Neutral-Point Clamped Voltage Source PWM Inverters”, IEEE Transactions on Power Electronics, Vol. 15, No. 2, pp. 154-162.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Online 15 15

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.