Analysis on Modified Booth 2n -1 Multipliers

Shalini*, P. Sampath**
* Research Scholar, ECE Department, Bannari Amman Institute of Technology, Sathyamangalam.
** Associate Professor, ECE Department, Bannari Amman Institute of Technology, Sathyamangalam.
Periodicity:August - October'2013
DOI : https://doi.org/10.26634/jcs.2.4.2472

Abstract

2 -1 is one of the commonly used moduli in Residue Number Systems. In this paper the power analysis on Radix-4 8-bit modified booth multiplier is made considering different parallel prefix adder structures. The technology used for the design of multiplier is 0.35μm CMOS technology. The parallel prefix adder structures that are included for the analysis are Kogge Stone adder, Brent Kung adder, Ladner Fischer adder etc. The analysis is made based on the power consumption made by the circuit and the total number of components (in terms of basic gates includes AND, OR and NOT) used for the design. It is found that multiplier structure with Ladner Fischer adder turn out to provide a better design with reduced power and basic gates required compared to other multiplier designs.

Keywords

Residue Number System (RNS), Booth Multipliers, Parallel Prefix Adders

How to Cite this Article?

Shalini, R. V., and Sampath, P. (2013). Analysis On Modified Booth 2n-1 Multipliers. i-manager’s Journal on Communication Engineering and Systems, 2(4), 1-6. https://doi.org/10.26634/jcs.2.4.2472

References

[1]. Soderstrand, M. A., et al.(1986). Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press.
[2]. Paliouras, V., and Stouraitis, T. (1999). Novel High-Radix Residue Number System Multipliers and Adders, Proc. IEEE Int'l Symp. Circuits and Systems. 451-454.
[3]. Wang, Y., et al. (2002). Adder Based Residue to Binary Number Converters for {2n - 1,2n, 2n +1}, IEEE Trans. Signal Processing. 50(7), 1772-1779.
[4]. Wang, W., et al. (2000). A High-Speed Residue-to-Binary Converter for Three- Moduli {2k, 2k - 1; 2k-1- 1}RNS and a Scheme for Its VLSI Implementation, IEEE Trans. Circuits and Systems II. 47(12), 1576-1581.
[5]. Skavantzos, A., and Rao, B. P.(1992). New Multipliers Modulo 2n -1, IEEE Trans. Computers, 41(8), 957-961.
[6]. Wang, Z., Jullien, G. A., and Miller, W. C. (1997). An Algorithm for Multiplication Modulo {2n - 1}, Proc. 39th Midwest Symp. Circuits and Systems. 1301- 1304.
[7]. Efstathiou, C., Vergos, H. T., and Nikolos, D. (2004). Modified Booth modulo 2n-1 multipliers, IEEE Trans. Comput. 53(3), 370–374.
[8 ]. Efstathiou, C., Nikolos, D., and Kalamatianos, J. (1994). Area-Time Efficient Modulo 2n-1 Adder Design, IEEE Trans. Circuits and Systems II, 41(7), 463-467.
[9]. Zimmerman, R. (1999). Efficient VLSI Implementation of Modulo {2n ± 1} Addition and Multiplication, Proc. 14th IEEE Symp. Computer Arithmetic, 158-167.
[10]. Kalampoukas, L., et al., (2000). High-Speed Parallel-Prefix Modulo 2n - 1 Adders, IEEE Trans. on Computers. 49(7), 673–680.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Online 15 15

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.