i-manager Publications

A Two Stage Power Optimized Implantable Neural Amplifier Based on Cascoded Structures

GuangleiAn*, Chris Hutchens**, Robert.L.Renneker II***

* PhD Student, MSVLSI Laboratory, School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma.

** MSVLSI Laboratory, School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, Oklahoma.

*** Department of Behavioral and Brain Sciences, Erik Jonsson School of Engineering, University of Texas at Dallas, Richardson, Texas.

Periodicity:June - August'2013
DOI : https://doi.org/10.26634/jcir.1.3.2441

Abstract

A low power, low noise of the two stage neural amplifier used in an intelligent Radio-Frequency Identification (RFID) based on folded cascode Operational Transconductance Amplifier (OTA) is presented. The optimization of the number of amplifier stages are discussed to achieve the minimum power and area consumption. The amplifier was submitted for fabrication in a 0.18 μm CMOS process. The amplifier power supply is 0.7V. The midband gain of amplifier is 58.4dB with a 3dB bandwidth from 0.71 to 8.26 kHz. Measured input-referred noise and total power consumption are 20.7μV rms and 1.90 μW respectively. The measured result shows that optimizing the number of stages can achieve lower power consumption and demonstrates the neural amplifier's suitability for instu neutral activity recording.

Keywords

Neural Signal, Low-Power Low-Noise Design, Optimized Power, Subthreshold Operation, Smart RFID

How to Cite this Article?

GuangleiAn, Hutchens, C., and Renneker II, R. L. (2013). Two Stage Power Optimized Implantable Neural Amplifier Based On Cascoded Structures. i-manager’s Journal on Circuits and Systems, 1(3), 1-7. https://doi.org/10.26634/jcir.1.3.2441

References

[1]. R. R. Harrison and C.Charles. (2003). A low-power low-noise CMOS amplifier for neural recording applications, Solid-State Circuits, IEEE Journal of, Vol. 38, pp. 958-965.

[2]. W. Wattanapanitch, M. Fee and R. Sarpeshkar. (2007). An Energy-Efficient Micropower Neural Recording Amplifier, Biomedical Circuits and Systems, IEEE Transactions on, Vol. 1, pp. 136-147.

[3]. K. Guillory and R. A. Normann. (1999). A 100-channel system for real time detection and storage of extracellular spike waveforms, Journal of Neurosci. Meth., Vol. 91, pp. 21-29.

[4]. Y. Ming and M. Ghovanloo. (2007). A Low-Noise Preamplifier with Adjustable Gain and Bandwidth for Biopotential Recording Applications, Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, pp. 321-324.

[5]. Y. Sitong, Johnson, L. G.,Liu, C. C.,Hutchens, C.,Rennaker, R. L. (2008). Current biased pseudo-resistor for implantable neural signal recording applications, Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on, pp. 658-661.

[6]. E. A. Vittoz. (2003). Weak inversion in analog and digital circuits.

[7]. Thomas.H.Lee. (2004). The Design of CMOS Radio -Frequency Integrated Circuits, Second ed.: Cambridge University Press.

[8]. R. J. Baker. (2007). CMOS Circuit Design, Layout, and Simulation, Revised Second Edition.

[9]. E. Vittoz. and X. Arreguit. (1993). Linear networks based on transistors, Electron. Lett., Vol. 29, pp. 297-299.

If you have access to this article please login to view the article or kindly login to purchase the article

Single Article

	North Americas,UK, Middle East,Europe		India	Rest of world
	USD	EUR	INR	USD-ROW
Online	15	15

ADD TO CART

Options for accessing this content:

If you would like institutional access to this content, please recommend the title to your librarian.
If you already have i-manager's user account: Login above and proceed to purchase the article.
New Users: Please register, then proceed to purchase the article.