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ASM Minimization for Digital Systems: Using GALS

Nasser Halasa*, Karim Al-jebory**

*Associate Professor, Dept. Of Computer Engineering, Applied Science University.

**Professor, Faculty of Engineering, Al Isra University.

Periodicity:October - December'2008
DOI : https://doi.org/10.26634/jse.3.2.242

Abstract

Control unit, in digital systems is one of the vital problems of optimal design. Several approaches of developing minimized modules for digital systems were studied. Algorithmic State Machine (ASM) has been analyzed by different approaches as coding the Excitation Function, coding the Input Logical Word and coding the Output Variables. This paper presents a modified method to synthesize the State Table (ST) of a digital system based on modifying the State Table Strings - rows. This new method results in minimizing the hardware used. Hardware Description Language (HDL) is the modern way for hardware design implementation, used in Programmable Logical Devices (PLD) such as Generic Array Logic (GAL) and Field-Programmable Gate Array (FPGA).The suggested method was tested and analyzed using Verilog HDL.

Keywords

Algorithmic State Machine (ASM), Generic Array Logic (GAL), Hardware Description Language (HDL), Digital Systems, States Minimization, Verilog, HDL

How to Cite this Article?

Nasser Halasa and Karim Al-jebory (2008). ASM Minimization for Digital Systems: Using Gals. i-manager’s Journal on Software Engineering, 3(2), 1-5. https://doi.org/10.26634/jse.3.2.242

References

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