A set of test vectors that detects all single stuck-at faults on all primary inputs of a fanout free combinational logic circuit will detect all single stuck –at faults in that circuit . A set of test vectors that detect all single stuck-at faults on all primary inputs and all fanout branches of a combinational logic circuit will detect all single stuck-at faults in that circuit. Design of logic integrated circuits in CMOS technology is becoming more and more complex since VLSI is the interest of many electronic IC users and manufactures . A common problem to be solved by designers, manufactures and users is the testing of these Ics. Testing can be expressed by checking if the outputs of a function systems (functional block, integrated circuits , printed circuit board or a complete systems) correspond to the inputs applied to it . If the test of this function system is positive , then the system is good for use. If the outputs are different than expected. Then the system has a problem : so either the system is rejected (go/no go test) , or a diagnosis is applied to it , in order to point out and probably eliminate the problem’s causes.