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Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme

A. Saisudheer*, V. Muralipraveen**

* M.Tech, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupathi, India.

** Assistant Professor, Department of ECE, Chadalawada Ramanamma Engineering College, Tirupathi, India.

Periodicity:December - February'2013
DOI : https://doi.org/10.26634/jcir.1.1.2195

Abstract

In this paper, a low-power pulse-triggered flip-flop (FF) designed and a simple two-transistor AND gate is designed to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various post layout simulation results based on UMC CMOS 50-nm technology reveal that the proposed design features the best power-delay-product performance in several FF designs under comparison. Its maximum power saving against rival designs is up to 18.2% and the average leakage power consumption is also reduced by a factor of 1.52

Keywords

Flip-flop, low power, pulse-triggered, pulse enhancement.

How to Cite this Article?

Saisudheer, A. and Muralipraveen, V. (2013). Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme. i-manager’s Journal on Circuits and Systems, 1(1), 16-21. https://doi.org/10.26634/jcir.1.1.2195

References

[1]. Yin-Tsung Hwang, Jin-Fa Lin, and Ming- Hwasheu, yin-Tsung Hwang, Jin-Fa Lin, And Ming-Hwasheu Manuscript “Low power pulse triggered flip flop design with conditional pulse enhancement scheme” received April 24,2010; revised August12,2010 and November 13, 2010; accepted November 16, 2010.Date of publication January 06, 2011; date of current version January 18, 2012.

[2]. H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, “Ultra low power clocking scheme using energy recovery and clock gating,” IEEE Trans. Very Large Scale Integer. (VLSI) Syst., Vol. 17, pp. 33–44, Jan.2009.

[3]. C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, “Conditional data mapping flip-flops for low power and high-performance systems,” IEEE Trans. Very Large Scale Integer. (VLSI) Systems, Vol.14, pp.1379–1383, Dec. 2006.

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[5]. S. H. Rasouli, A. Khademzadeh, A. Afzali-Kusha, and M. Nourani,“ Low power single- and double-edge-triggered flip-flops for high speed applications,” Proc. Inst. Electr. Eng.—Circuits Devices Syst., vol. 152, no. 2, pp. 118–122, Apr. 2005.

[6]. P. Zhao, T. Darwish, and M. Bayoumi, “High-performance and low power conditional discharge flip-flop,” IEEE Trans. Very Large Scale Integer. (VLSI) Syst., Vol. 12, No. 5, pp. 477–484, May 2004.

[7]. V. G. Oklobdzija, “Clocking and clocked storage elements in a multigiga-hertz environment,” IBM J. Res. Devel., Vol. 47, pp. 567–584, Sep.2003.

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Reducing Clock Power Wastage By Using Conditional Pulse Enhancement Scheme

Abstract

Keywords

How to Cite this Article?

References

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