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Design of Reversible Full Adder or Subtractor Based on EPOE Expressions for Computational Applications

Rama Krishna Reddy E.*, Aashrutha Sai Pushpa F. P**, Bala Nageswari G. G.***, H. S. S. H. V. P. Rahul Vijay****, Adithya I. A.*****

*-***** Usha Rama College of Engineering and Technology, Telaprolu, Andhra Pradesh, India.

Periodicity:July - September'2025

Abstract

Reversibility plays a crucial role in achieving energy-efficient computations.This study proposes the design of low-cost self-control serial adder system is proposed, utilizing EPOE expression for the efficient and streamlined design of sequential circuits. This approach aims in minimizing the fixed inputs in sequential logic circuits and reduce quantum cost, common terms between outputs are optimally shared. Additionally, limiting the use of Tofoli gates with more than three inputs in the final circuit implementation helps lower the quantum cost of the resulting circuit.

Keywords

Reversibility, Serial Adder, Self-Control, Fredkin Gate, EPOE.

How to Cite this Article?

Reddy, E. R. K., Pushpa, F. P. A. S., Nageswari, G. G. B., Vijay, H. S. S. H. V. P. R., and Adithya, I. A. (2025). Design of Reversible Full Adder or Subtractor Based on EPOE Expressions for Computational Applications. i-manager’s Journal on Electronics Engineering, 15(4), 10-20.

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Design of Reversible Full Adder or Subtractor Based on EPOE Expressions for Computational Applications

Abstract

Keywords

How to Cite this Article?

References

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