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Design of a Robust Controller for the Load Frequency Control of Interconnected Power System

Ch. Naga Sai Kalyan*

Department of Electrical and Electronics Engineering, Vasireddy Venkatadri Institute of Technology, Andhra Pradesh, India.

Periodicity:April - June'2024
DOI : https://doi.org/10.26634/jps.12.1.21152

Abstract

This paper aims to develop a robust (1+PD)-PID cascade controller for the frequency stabilization of a multi-area Interconnected Power System (IPS). The operational performance of the proposed controller is studied by introducing a Step Load Disturbance (SLD) of 10% in area 1 of the considered power system model. For fine-tuning the proposed controller, the Butterfly Optimization Algorithm (BFOA) is employed. The superior performance of the proposed controller is validated against other controllers available in the literature. Furthermore, to enhance power system performance, a High-Voltage DC (HVDC) line is implemented in the test system model. The simulation results confirm the improvement in system performance with the incorporation of the HVDC line. To assess the robustness of the proposed controller, a sensitivity test is conducted, which validates its robustness.

Keywords

(1+PD)-PID Cascade Controller, Butterfly Optimization Algorithm, Frequency Stabilization, Interconnected Power System, 10% Step Load Disturbance.

How to Cite this Article?

Ch. Kalyan, N. S. (2024). Design of a Robust Controller for the Load Frequency Control of Interconnected Power System. i-manager’s Journal on Power Systems Engineering, 12(1), 54-66. https://doi.org/10.26634/jps.12.1.21152

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