Limited Drive Reaction channels are the most significant component in signal handling and correspondence. The architecture of a FIR filter includes a delay unit, multiplier, and adder. Along these lines, execution of FIR channel is chiefly founded on multiplier. In this paper we present FIR channel execution of Wallace multiplier. Delay, power, and Area's performance can all be improved with this method. VHDL is used to write the code, which is simulated using ModelSim 6.3c and synthesized using Xilinx ISE 9.2i. The design is then put into action in the Spartan-3 FPGA.