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Performance and Analysis of Different Adder Topologies

Rashmi B. K.*, Rohith J.**, Shreya Suresh Mudaladavar***, Supreet Hosageri****, Mahantesh P. Mattada*****

*-***** Department of Electronics and Communication Engineering, PES Institute of Technology and Management, Shivamogga, India.

Periodicity:April - June'2024
DOI : https://doi.org/10.26634/jele.14.3.20675

Abstract

This paper gives an overview of area, power, delay for four different 64-bit adders. The design metrics in VLSI are low area and delay alongside low power designs. Adder is one of the necessary components of almost every kind of digital and high- performance systems such as FIR filters, digital signal processors and microprocessors etc. Different types of adders are carry tree adder, carry save adder, carry look ahead adder and carry select adder. In this work we have designed, simulated and synthesized these adder topologies and compared the results in cadence tool.

Keywords

Carry Look Ahead Adder, Carry Save Adder, Carry Tree Adder, Full Adder.

How to Cite this Article?

Rashmi, B. K., Rohith, J., Mudaladavar, S. S., Hosageri, S., and Mattada, M. P. (2024). Performance and Analysis of Different Adder Topologies. i-manager’s Journal on Electronics Engineering, 14(3), 31-37. https://doi.org/10.26634/jele.14.3.20675

References

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Performance and Analysis of Different Adder Topologies

Abstract

Keywords

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References

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