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Review on Multi Bit Flip-Flop Enhanced Shift Register: A Low Power Solution for UART

Swathi Prabhu*, Unnathi H. R.**, Chethan B. R.***, Tejaswini R.****, Vaishnavi A. O.*****

*-***** Electronics & Communication Engineering, PES Institute of Technology and Management, India.

Periodicity:October - December'2023
DOI : https://doi.org/10.26634/jee.17.2.20432

Abstract

This paper details the Verilog HDL- based design of UART modules. Developing UART with a shift register utilizing multibit flip-flops proves to be pragmatic strategy for contemporary VLSI circuits. This work supports not only asynchronous and serial communication but also aligns with essential objectives of minimizing power consumption and reducing overall circuit area. Such integration enhances data transmission efficiency while meeting crucial design considerations in modern electronics.

Keywords

Shift Register, Multi-Bit Flip-Flop, UART, Xilinx, Cadence.

How to Cite this Article?

Prabhu, S., Unnathi, H. R., Chethan, B. R., Tejaswini, R., and Vaishnavi, A. O. (2023). Review on Multi Bit Flip-Flop Enhanced Shift Register: A Low Power Solution for UART. i-manager’s Journal on Electrical Engineering, 17(2), 35-39. https://doi.org/10.26634/jee.17.2.20432

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