i-manager Publications

Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems

S. Divya*

Department of Electronics and Communication Engineering, Sphoorthy Engineering College, Hyderabad, Telangana, India.

Periodicity:July - December'2023
DOI : https://doi.org/10.26634/jcir.11.2.20398

Abstract

This paper explores efficient logic cell design strategies for ultralow-energy subthreshold operation in wearable biomedical systems. Traditional logic cell design approaches often lead to suboptimal efficiency due to unbalanced Pull-Up (PU) and Pull-Down (PD) networks. Various techniques are examined, including balanced PU/PD network design using body biasing and statistical distribution analysis of drain-source current. Moreover, the reverse channel (RSC) effect is investigated for device optimization. Single-stage gates such as inverters, NAND, and NOR gates are designed with Mentor Graphics tools to minimize power dissipation and area. Multistage gates like XOR and XNOR gates are also optimized for reduced signal propagation delay. A detailed analysis of D-flip-flop designs with varying transistor counts is presented. Power dissipation, delay, rise time, and fall time characteristics are compared for flip-flop configurations comprising 18, 10, and 5 transistors. The results indicate significant energy optimization with the proposed designs, particularly with the 5-transistor configuration, demonstrating the effectiveness of the proposed methodologies in achieving superior energy efficiency and reduced signal noise in biomedical systems.

Keywords

Finite Impulse Response (FIR), Inverse Narrow Width (INW), Ultralow Energy, Ultralow Voltage, Subthreshold Operation, Logic Cell Design, D Flip-Flop.

How to Cite this Article?

Divya, S. (2023). Efficient Logic Cell Design for Ultralow-Energy Subthreshold Operation in Wearable Biomedical Systems. i-manager’s Journal on Circuits and Systems, 11(2), 20-26. https://doi.org/10.26634/jcir.11.2.20398

References

[1]. Akers, L. A. (1986). The inverse-narrow-width effect. IEEE Electron Device Letters, 7(7), 419-421.

[2]. Alioto, M. (2010). Understanding DC behavior of subthreshold CMOS logic through closed-form analysis. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(7), 1597-1607.

[3]. Calhoun, B. H., & Chandrakasan, A. (2004, August). Characterizing and modeling minimum energy operation for subthreshold circuits. In Proceedings of the 2004 International Symposium on Low Power Electronics and Design (pp. 90-95).

[4]. Chanda, M., Jain, S., De, S., & Sarkar, C. K. (2015). Implementation of subthreshold adiabatic logic for ultralow-power application. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(12), 2782-2790.

[5]. Chang, I. J., Park, S. P., & Roy, K. (2010). Exploring asynchronous design techniques for process-tolerant and energy-efficient subthreshold operation. IEEE Journal of Solid-State Circuits, 45(2), 401-410.

[6]. Dorosti, H., Teymouri, A., Fakhraie, S. M., & Salehi, M. E. (2015). Ultralow-energy variation-aware design: Adder architecture study. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(3), 1165-1168.

[7]. Frustaci, F., Corsonello, P., & Perri, S. (2012). Analytical delay model considering variability effects in subthreshold domain. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(3), 168-172.

[8]. Hanson, S., Seok, M., Sylvester, D., & Blaauw, D. (2007). Nanometer device scaling in subthreshold logic and SRAM. IEEE Transactions on Electron Devices, 55(1), 175-185.

[9]. Hwang, M. E., Raychowdhury, A., Kim, K., & Roy, K. (2007, June). A 85mV 40nW process-tolerant subthreshold 8× 8 FIR filter in 130nm technology. In 2007 IEEE Symposium on VLSI Circuits (pp. 154-155). IEEE.

[10]. Kim, T. H., Eom, H., Keane, J., & Kim, C. (2006, October). Utilizing reverse short channel effect for optimal subthreshold circuit design. In Proceedings of the 2006 International Symposium on Low Power Electronics and Design (pp. 127-130).

[11]. Klinefelter, A. M., Zhang, Y., Otis, B., & Calhoun, B. H. (2012). A programmable 34 nW/channel sub-threshold signal band power extractor on a body sensor node SoC. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 937-941.

[12]. Li, M. Z., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., & Martins, R. P. (2013, July). Sub-threshold standard cell librar y design for ultra-low power biomedical applications. In 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) (pp. 1454-1457). IEEE.

[13]. Li, M. Z., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., Pun, S. H., & Martins, R. P. (2015). Energy optimized subthreshold VLSI logic family with unbalanced pullup/down network and inverse narrow-width techniques. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(12), 3119-3123.

[14]. Li, M. Z., Ieong, C. I., Law, M. K., Mak, P. I., Vai, M. I., Pun, S. H., & Martins, R. P. (2016, January). Sub-threshold VLSI logic family exploiting unbalanced pull-up/down network, logical effort and inverse-narrow-width techniques. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 15-16). IEEE.

[15]. Liu, B., Pineda de Gyvez, J., & Ashouei, M. (2013). Sub-threshold standard cell sizing methodology and library comparison. Journal of Low Power Electronics and Applications, 3(3), 233-249.

[16]. Ma, W. H., Kao, J. C., Sathe, V. S., & Papaefthymiou, M. C. (2010). 187 MHz subthreshold-supply chargerecovery FIR. IEEE Journal of Solid-State Circuits, 45(4), 793-803.

[17]. Markovic, D., Wang, C. C., Alarcon, L. P., Liu, T. T., & Rabaey, J. M. (2010). Ultralow-power design in nearthreshold region. Proceedings of the IEEE, 98(2), 237-252.

[18]. Reynders, N., & Dehaene, W. (2012). Variationresilient building blocks for ultra-low-energy sub-threshold design. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 898-902.

[19]. Sutherland, I., Sproull, R. F., & Harris, D. (1999). Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann, San Francisco.

[20]. Wang, J. M., Fang, S. C., & Feng, W. S. (1994). New efficient designs for XOR and XNOR functions on the transistor level. IEEE Journal of solid-state Circuits, 29(7), 780-786.

[21]. Zhang, F., Mishra, A., Richardson, A. G., Zanos, S., & Otis, B. P. (2010, September). A low-power multi-band ECoG/EEG interface IC. In IEEE Custom Integrated Circuits Conference 2010 (pp. 1-4). IEEE.

[22]. Zhou, J., Jayapal, S., Busze, B., Huang, L., & Stuyt, J. (2012). A 40 nm dual-width standard cell library for near/sub-threshold operation. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(11), 2569-2577.

If you have access to this article please login to view the article or kindly login to purchase the article

Single Article

	North Americas,UK, Middle East,Europe		India	Rest of world
	USD	EUR	INR	USD-ROW
Online	15	15

ADD TO CART

Options for accessing this content:

If you would like institutional access to this content, please recommend the title to your librarian.
If you already have i-manager's user account: Login above and proceed to purchase the article.
New Users: Please register, then proceed to purchase the article.