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Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture

Rajkumar K.*

Department of Electrical Engineering, Shri Shankaracharya Group of Institution, Junwani, Chhattisgarh, India.

Periodicity:July - December'2023
DOI : https://doi.org/10.26634/jcir.11.2.20397

Abstract

Arithmetic Logic Units (ALUs) are key elements within processors, executing a variety of operations including multiplication, division, addition, and subtraction. Among these, multiplication stands out as the most frequently utilized function within ALUs. This study presents an innovative MSI-interfaced multiplier architecture designed for integration into a multi-precision floating-point multiplier framework. This novel architecture offers configurations for 24-bit, 53-bit, 113- bit, and 237-bit binary operations, corresponding to single, double, quadruple, and octuple precision modes of floating-point computation. Notably, it enhances throughput by accommodating the multiplication of multiple batches of inputs with each operation initiation, surpassing existing binary multiplication systems. A unique Mantissa Similarity Investigation (MSI) implementation is developed and integrated into the binary multiplier architecture. Comparative analysis of the path delay in 24-bit mode against existing 24-bit multipliers demonstrates that the novel MSI-interfaced binary multiplier architecture, with and without MSI, exhibits reduced path delay compared to all existing systems, as anticipated.

Keywords

Arithmetic Logic Unit, Binary Multiplier, MSI-Interfaced Multiplier System, Multiplier Architecture, FPGAs in Arithmetic.

How to Cite this Article?

Rajkumar, K. (2023). Design and Optimization of MSI-Enabled Multi-Precision Binary Multiplier Architecture. i-manager’s Journal on Circuits and Systems, 11(2), 27-35. https://doi.org/10.26634/jcir.11.2.20397

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