The increasing demand for high-density Very Large-Scale Integrated (VLSI) circuits, driven by the scaling of CMOS technology, is primarily challenged by the need for uniformity in SRAM cells. Given that most programs frequently seek dependable data, the primary cache and memory caching (MC) component in SRAM tends to be relatively steady. Resolving power and delay imbalances is the main problem with SRAM cells. The issues with CMOS-based SRAM cells include high cost, wide parameter variation, and worse dependability. CMOS devices also experience a loss of channel control by the gate. It is therefore advised to use FinFET-based SRAM cells rather than CMOS. This paper presents a design study of a 1T-1D SRAM cell using FinFET and CMOS technology. Without changing the logic state of the SRAM cell, the objective of this paper is to lessen power leakage. The cell structure's ease of design also contributes to its remarkable affordability and accessibility. A 1T-1D cell with the bare minimum of transistors has a smaller overall area. The suggested 1T-1D SRAM cell is implemented using the Tanner EDA working platform, which uses 7nm FinFET technology. With this study, low power was reached up to 99%, and delay reduction was improved to 98%.