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Design of Duty Cycle Correction Circuit using ASIC Implementation for High Speed Communication

Siddesh K. B.*, Roopa S.**, Farzana Parveen B. A.***, Tanuja T.****

*-**** Department of Electronics and Communication Engineering, Sri Jagadguru Murugarajendra Institute of Technology, Chitradurga, Visvesvaraya Technological University, Karnataka, India.

Periodicity:April - June'2023
DOI : https://doi.org/10.26634/jele.13.3.19969

Abstract

This research proposed an accurate Duty Cycle Correction (DCC) circuit for high-frequency systems with high measurement accuracy. It is a crucial component of Very Large Scale Integration (VLSI) circuits and is applied as a percentage of the measured average power of a modulated signal to obtain the signal power. This circuit uses two stages of correction, with the first stage performing course correction and the second stage performing fine corrections. This allows the power to be determined during the pulse given the measurement of the average power of a modulated signal with a known duty cycle. DCC have improved stability, correction range, and operating frequency compared with mixed-signal and all-digital DCCs. In this analysis, the duty cycle correction circuits and their significance in Application Specific Integrated Circuit (ASIC) design, along with typical implementation methods, are discussed.

Keywords

Duty Cycle, Multiplexer, Clock, Delay Line, Application Specific Integrated Circuit (ASIC), Very Large Scale Integration (VLSI).

How to Cite this Article?

Siddesh, K. B., Roopa, S., Parveen, B. A. F., and Tanuja T. (2023). Design of Duty Cycle Correction Circuit using ASIC Implementation for High Speed Communication. i-manager’s Journal on Electronics Engineering, 13(3), 33-39. https://doi.org/10.26634/jele.13.3.19969

References

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Design of Duty Cycle Correction Circuit using ASIC Implementation for High Speed Communication

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