i-manager Publications

Boosting Chip Verification Efficiency: UVM-Based Adder Verification with QuestaSim

Niharika Sahu*, Chandrahas Sahu**

*-** Department of Electronics and Telecommunication, Shri Shankaracharya Technical Campus, Bhilai, India.

Periodicity:January - June'2023
DOI : https://doi.org/10.26634/jdp.11.1.19768

Abstract

The Very Large-Scale Integration (VLSI) industry is currently experiencing rapid growth in chip verification and design. This research focuses on generating a waveform, simulating, and verifying the Universal Verification Methodology (UVM) adder code using the QuestaSim tool and the UVM methodology. The functional verification community and researchers have an interest in UVM as it offers flexibility, reusability, and reliability properties that are useful for verifying complex chip systems. The main objective of this research is to verify the code of the UVM adder using the QuestaSim tool, which is a widely used tool for verifying digital circuits. Additionally, it aims to demonstrate the effectiveness of using the UVM methodology in verifying complex chip systems and highlights the importance of developing reliable and efficient verification methods for the VLSI industry.

Keywords

System Verilog, UVM Methodology, Adder, Verification.

How to Cite this Article?

Sahu, N., and Sahu, C. (2023). Boosting Chip Verification Efficiency: UVM-Based Adder Verification with QuestaSim. i-manager’s Journal on Digital Signal Processing, 11(1), 16-21. https://doi.org/10.26634/jdp.11.1.19768

References

[1]. Barbe, D. F. (Ed.). (2013). Very Large Scale Integration (VLSI): Fundamentals and Applications (Vol. 5). Springer Science & Business Media.

[2]. Francesconi, J., Rodriguez, J. A., & Julian, P. M. (2014, July). UVM based testbench architecture for unit verification. In 2014 Argentine Conference on MicroNanoelectronics, Technology and Applications (EAMTA) (pp. 89-94). IEEE.

[3]. Garg, A., & Joshi, G. (2018). Gate diffusion input based 4 bit Vedic multiplier design. IET Circuits, Devices & Systems, 12(6), 764-770.

[4]. Kumar, J. S., Konathala, R., Manikandan, R., Ramesh, C., & Rahim, R. (2019). Design and UVM verification of high speed ALU. International Journal on Emerging Technologies, 10(1), 93-96.

[5]. Patel, R. (2021). UVM – Introduction.

[6]. Salah, K. (2014, December). A UVM-based smart functional verification platform: Concepts, pros, cons, th and opportunities. In 2014 9 International Design and Test Symposium (IDT) (pp. 94-99). IEEE.

[7]. Shen, H., & Zhong, C. (2022). A Universal-VerificationMethodology-Based Verification Strategy for High-Level Synthesis Design (Master's thesis, Chalmers University of Technology).

[8]. Sutherland, S., & Fitzpatrick, T. (2015). UVM rapid adoption: A practical subset of UVM. In 2015 Design and Verification Conference & Exhibition (pp. 1-28).

[9]. Verificationguide. (n.d.). System Verilog Test Bench Example-Adder.

[10]. Verificationguide. (n.d.). UVM Testbench.

[11]. Yadav, Y., & Chawla, M. (2018). A review on adders in digital circuits. Journal of Emerging Technologies and Innovative Research, 5(6), 64-65.

If you have access to this article please login to view the article or kindly login to purchase the article

Single Article

	North Americas,UK, Middle East,Europe		India	Rest of world
	USD	EUR	INR	USD-ROW
Online	15	15

ADD TO CART

Options for accessing this content:

If you would like institutional access to this content, please recommend the title to your librarian.
If you already have i-manager's user account: Login above and proceed to purchase the article.
New Users: Please register, then proceed to purchase the article.