Development of a 4-Digit BCD Multiplier Architecture with Similarity Investigator

Marcus Lloyde George*
University of the West Indies, St Augustine, Trinidad and Tobago.
Periodicity:January - March'2023


Arithmetic Logic Units (ALUs) are very important components in computer systems. They are digital circuits utilized to perform a wide variety of arithmetic and logic operations. Modern Central Processing Units (CPUs) contain powerful and complex ALUs. One such operation performed by ALUs is that of Multiplication. Multiplication scales one variable by another. This research involves the design, implementation and verification of a 4-digit BCD Multiplier Core with Similarity Investigator for path delay reduction. The system is implemented using Xilinx ISE 14.7, verified using ISim and Digilent Nexy3 toolkit and was utilized as the development platform. The research concluded that similarity investigation was capable of path delay reduction of up to 97% compared to that when no similarity investigation was applied. The system can conduct a maximum of 889 unique multiplication operations before facing diminishing returns as a result of the similarity investigation search procedure.


Arithmetic Logic Unit, Binary Coded Decimal, BCD Multiplier, BCD Multiplication, Similarity Investigation.

How to Cite this Article?

George, M. L. (2023). Development of a 4-Digit BCD Multiplier Architecture with Similarity Investigator. i-manager’s Journal on Electronics Engineering, 13(2), 1-17.


[15]. Kumar, N., Bansal, M., & Kumar, N. (2012). VLSI architecture of pipelined booth Wallace MAC unit. International Journal of Computer Applications, 57(11), 14-18.
[19]. Pawlak, A., Bouchard, F., & Bakowski, P. (1997, April). Survey on VHDL Modelling Guidelines. In Proceedings of the 2nd Workshop on Libraries, Component Modeling, and Quality Assurance, Toledo, Spain (pp. 117-128).
[20]. Perry, D. L. (1998). VHDL. McGraw-Hill, New York.
[24]. Tsang, A., & Olschanowsky, M. (1991). A study of database 2 customer queries. IBM Santa Teresa Laboratory, San Jose, CA.
[26]. Vazquez, A., & de Dinechin, F. (2010b). Multioperand decimal tree adders for FPGAs. Institut National de Recherche en Informatique et en Automatique (pp. 1-20).
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