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A High-Performance Energy Efficient Packet Classification Design on FPGA

Midde Adiseshaiah*, Maruvada Sailaja**

*-** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Kakinada, Andhra Pradesh, India.

Periodicity:January - June'2023
DOI : https://doi.org/10.26634/jcs.12.1.19414

Abstract

One of the most crucial thing to safeguard the network against malicious activities is security and the network devices must be able to classify packets. The firewall applications benefit greatly from the architecture of the packet classification engine that is given in this research work. A tree-based approach is used to systematically analyze each field in a packet header, leading to a more secure system. The Packet Classification Engine (PCE) is configured to evaluate Ethernet packets based on the source IP address, destination IP address, source port, destination port, and protocol aspects in the packet header. The PCE shows that the typical clock frequency from input to output is 13 clocks per second. The architecture is extremely rapid, reliable, and adaptable and can make good use of the tree based algorithm's advantages. The proposed architecture has achieved high throughput of 538 MPPS with less energy of 10.6 nJ at low latency of 62 ns. The PCE must have a rapid and reliable FIFO buffer to work effectively. A FPGA (Field Programmable Gate Array) device is being utilized to filter Ethernet packets using the proposed PCE.

Keywords

Packet Classification, FPGA, Tree-Based Algorithm.

How to Cite this Article?

Adiseshaiah, M., and Sailaja, M. (2023). A High-Performance Energy Efficient Packet Classification Design on FPGA. i-manager’s Journal on Communication Engineering and Systems, 12(1), 24-30. https://doi.org/10.26634/jcs.12.1.19414

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