References
[1]. P. Vipeesh and N.J.R. Muniraj, (2011). “Development
and validation of Matlab models for nanowire sensors”,
Communications in Computer and Information Science,
(2011), pp. 270–283. © Springer-Verlag Berlin Heidelberg.
[2]. P. Vipeesh and N.J.R. Muniraj, “Design and modelling
PSA detection for prostate cancer using 8 x 8 sensor array”,
Int. J. Biomedical Engineering and Technology, accepted.
[3]. Rajendra Katti, (l994). “A Modified Booth Algorithm for
High Radix Fixed-point Multiplication”, IEEE Transactions
On Very Large Scale Integration (VLSI) Systems, Vol 2, No
1, December.
[4]. A. Booth, (1951). “A signed binary multiplication
technique,” Q. J. Me & Appl. Marh., Vol. 4, pp. 236-240.
[5]. P. E. Madrid, B. Millar, and E. E. Swartzlander, (1993).
“Modified Booth algorithm for high radix fixed-point
multiplication,” IEEE Trans. VLSI Sysr., Vol. I, No. 2, pp. 164-
167, June.
[6]. Shyh-Jye Jou, Chang-Yu Chen, En-Chung and Chau-
Chin Su (2000). “A Pipeline Multiplier-Accumulator Using a
High Speed Low-Power Static and Dynamic Full Adder”
Journal of Solid State Circuits, Vol 32, No-1, January.
[7]. C. S. Wallace, (1964). “A suggestion for fast
multipliers,” IEEE Trans. Electron. Computers, Vol. 13, pp.
14-17, Feb.
[8]. M. R. Santoro and M. A. Horowitz, (1989). “SPIM: a
pipelined 64×64- bit iterative multiplier,” IEEE J. Solid-State
Circuits, Vol.24, No. 2, pp. 487-493, Apr.
[9]. B-I. Park, I-C. Park, and C-M. Kyung, (1999). “A regular
layout structured multiplier based on weighted carry-save
adders,” Proc. IEEE International Conference on
Computer Design, pp.243-248, Oct.
[10]. J. Yuan and C. Svensson, (1989). “High-speed CMOS
circuit technique,” IEEE J. Solid-State Circuits, Vol. 24, No.
1, pp. 62- 70, Feb.
[11]. C. Seitz, (1980). “System timing,” in Introduction to
VLSI Systems, C. Mead and L. Conway, Addison-Wesley.
[12]. A. D. Booth, (1951). “A signed binary multiplication
technique,” Quarter. J. Mech. Appl. Math., Vol. 4, part 2,
pp. 236-240.
[13]. N. Ohkubo, et al., (1995). “A 4.4ns CMOS 54×54-b multiplier using pass-transistor multiplexer,” IEEE J. Solid-
State Circuits, Vol. 30, No. 3, pp. 251-257, Mar.
[14]. KiamalZ. Pekmestzi, (1999). “Multiplexer-Based Array
Multipliers”, IEEE Transactions on Computers, Vol. 48, No.
1, January.
[15]. PedramMokrian, (2003). “A Reconfigurable Digital
Multiplier Architecture” A Master's Thesis, Department of
Electrical and Computer Engineering, University of
Windsor, April.
[16]. Gary W. Bewick, (1994). “Fast Multiplication:
Algorithms and Implementation”, A Ph.D Dissertation,
Stanford University.
[17]. D. Radhakrishnan, (1999). “Low Voltage CMOS Full
Adder Cells,”Electronics Letters, Vol. 35, pp. 1792-94,
October.
[18] . Anant Yogeshwar Chitari, (2000). “VLSI Architecture
for a 16-bit Multiply-Accumulator (MAC) Operating in
Multiplication Time”, A Master's Thesis, Department of
Electrical Engineering, Texas A&M University –Kingsville,
May.
[19]. Behrooz Parhami, (2000). “Computer Arithmetic:
Algorithms and Hardware Designs”, Oxford University
Press, New York.