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Leakage Power Optimization using Sleeping Approaches in TSPC D Flip-Flop

Varun*, Bal Krishan**, Rohit Tripathi***

*-*** Department of Electronics Engineering, YMCA University of Science and Technology, Faridabad, Haryana, India.

Periodicity:July - December'2022
DOI : https://doi.org/10.26634/jcir.10.2.18978

Abstract

In this paper, the basic D flip-flop has been considered with TSPC (True Single-Phase Clock) logic. Here, the leakage power of 1031 pW fell to the power for the operation of the memory elements, which is a lot compared to other triggers. The challenge is to reduce the optimal power off to conserve idle power. To solve this problem, three different powersaving techniques were considered, such as Technique 1: sleeping transistors, Technique 2: sleepy stack, and Technique 3: sleepy keeper. In a comparative study, it was observed that Technique 1 is the most optimal method for delays (falling and rising) and off-state leakage power compared to the other methods considered. The off-state leakage power was 1.753 pW, which is 93.07% and 76.90% less than by Techniques 2 and 3, respectively.

Keywords

TSPC D Flip-Flop, Sub-Threshold, Optimum Power, Recovery Speed.

How to Cite this Article?

Varun, Krishan, B., and Tripathi, R. (2022). Leakage Power Optimization using Sleeping Approaches in TSPC D Flip-Flop. i-manager’s Journal on Circuits and Systems, 10(2), 10-18. https://doi.org/10.26634/jcir.10.2.18978

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