Development of a Control Path VHDL Code Generator for Hardware Development

Marcus Lloyde George*, Brandon Joseph**
*-** Department of Electrical and Computer Engineering, University of the West Indies, St. Augustine, Trinidad, Tobag.
Periodicity:January - March'2022
DOI : https://doi.org/10.26634/jse.16.3.18660

Abstract

The Very High-Speed Integration Circuit HDL (VHDL) is widely used to implement digital electronic systems. The VHDL language can be difficult to learn, so it is necessary to simplify and speed up the process of implementing digital electronic components through a hardware description with a minimal understanding of the VHDL language. This paper entails the design and development of a Graphical User Interface (GUI) capable of generating VHDL code for ControlPaths using specified state transition tables and state diagrams. This application was created using the Matrix Laboratory (MATLAB). Application Builder as the development platform. After development, the system went through unit testing and integration testing, after which acceptance testing was carried out. The results of the acceptance tests showed that the software is very effective in quickly generating VHDL code for ControlPaths.

Keywords

Code Generators, VHDL, Hardware Description Language, Hardware Design, Digital Logic Design, ControlPath, Finite State Machine.

How to Cite this Article?

George, M. L., and Joseph, B. (2022). Development of a Control Path VHDL Code Generator for Hardware Development. i-manager’s Journal on Software Engineering, 16(3), 16-45. https://doi.org/10.26634/jse.16.3.18660

References

[1]. Areno, M. C. (2007). Automated Constraint-Based Hardware Architecture Generation For Reconfigurable Computing Systems. Utah State University.
[2]. Davis, B. (2018). Is VHDL easy to learn? Retrieved from https://www.mvorganizing.org/is-vhdl-easy-to-learn/
[3]. Franky, M. C., & Pavlich-Mariscal, J. A. (2012, October). Improving implementation of code generators: A regular-expression approach. In 2012 XXXVIII Conferencia Latinoamericana En Informatica (CLEI) (pp. 1-10). IEEE. https://doi.org/ 10.1109/CLEI.2012.6427199
[4]. Hamdan, M. K. (2018). VHDL Auto-Generation Tool for Optimized Hardware Acceleration of Convolutional Neural Networks on FPGA (VGT) (Doctoral dissertation, Iowa State University).
[5]. Kalage, A. A., Jape, V. M., Tade, S. V., Hapse, M. M., & Dabhade, R. G. (2009). Modeling and simulation of FPGA based direct torque control of induction motor drive. International Journal of recent trends in Engineering, 1(4), 72-74.
[6]. Loniewski, G., Insfran, E., & Abrahão, S. (2010, October). A systematic review of the use of requirements engineering techniques in model-driven development. In International Conference on Model Driven Engineering Languages and Systems (pp. 213-227). Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-16129-2_16
[7]. Sejans, J., & Nikiforova, O. (2011). Practical Experiments with Code Generation from the UML Class Diagram. In Proceedings of the 3rd International Workshop on Model-Driven Architecture and Modeling-Driven Software Development (pp. 57-67). https://doi.org/10.5220/0003581300570067
[8]. Susanti, A. R. D., Thoyib, W., & Schumann, T. (2011, July). Development of a reliable GUI for DiaHDL: A webbased VHDL code generator. In Proceedings of the 2011 International Conference on Electrical Engineering and Informatics (pp. 1-5). IEEE. https://doi.org/10.1109/ICEEI.2011.6021819
[9]. Syromiatnikov, A., & Weyns, D. (2014, April). A journey through the land of model-view-design patterns. In 2014 IEEE/IFIP Conference on Software Architecture (pp. 21-30). IEEE. https://doi.org/10.1109/WICSA.2014.13
[10]. Thompson, H. A., Ramos-Hernandez, D., Fu, J., Jiang, L., Nu, J., & Dobinson, D. (2008). The FLEXICON cosimulation tools applied to a marine application. Proceedings of the Institution of Mechanical Engineers, Part M: Journal of Engineering for the Maritime Environment, 222(2), 81-94. https://doi.org/10.1243/14750902JEME78
[11]. Tselepis, I. N., & Bekakos, M. P. (2006, April). VHDL Code Automatic Generator for Systolic Arrays. In 2006 2nd International Conference on Information & Communication Technologies (Vol. 2, pp. 2330-2334). IEEE. https://doi.org/10.1109/ICTTA.2006.1684770
[12]. Uttar. (2021). SDLC (Software Development Life Cycle) Phases, Process, Models – Complete guide. Retrieved from https://www.scmgalaxy.com/tutorials/ sdlc-software-development-life-cycle-phases-processmodels-complete-guide/
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