Low Power SRAM Cell Design with Power Gating Technique

V. Seetha*
Department of Electronics and Communication Engineering, Meenakshi Ramaswamy Engineering College, Ariyalur, Tamil Nadu, India.
Periodicity:January - June'2022
DOI : https://doi.org/10.26634/jcir.10.1.18569

Abstract

The power consumption of Static Random-Access Memory (SRAM) cell is considered as a major factor in modern technologies due to voltage scaling. The existing SRAM cell design of consumes more power at higher frequencies. In the proposed work, power reduction is achieved in various radiation-hardened SRAM cell designs which is based on power gating technique. Hence, the power gated voltage (VDD) design technique is employed to reduce power consumption.

Keywords

SRAM, Power Gating, Low Power Technique, Radiation Hardening by Design (RHBD).

How to Cite this Article?

Seetha, V. (2022). Low Power SRAM Cell Design with Power Gating Technique. i-manager’s Journal on Circuits and Systems, 10(1), 25-34. https://doi.org/10.26634/jcir.10.1.18569

References

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