In this paper we present a procedure to study the effects of parasitic elements (capacitances, inductances and resistances) of interconnection lines in integrated circuits where Carbon Nanotubes are embedded. In particular the Drain/Source pads dimensions of CNT are analysed, as well as the interconnection lines between a CNT and an appropriate load are sized. In order to estimate parasitic elements in CNTs embedded integrated circuits, we analyse 50 nm technology. Moreover it is also possible for predictions analysis on 10 nm and 3 nm technology. We apply the proposed procedure to the design of a Common-Source amplifier, using a CNTFET model already proposed by us. The frequency domain simulations, obtained using the ADS simulator, show how the parasitic elements limit the performances of CNTs. In particular we obtain that the -3 dB cutting frequency of the examined amplifier full of parasitic elements increases as technology decreases. Moreover we repeat the proposed simulations using SPICE, obtaining results practically coincident but with the Verilog-A implementation we have mainly a simulation run time much shorter and a software much more concise and clear than schemes using ABM blocks in SPICE.