A Review on FPGA Based Design of Advanced Encryption Standard (AES) Cryptography Secure Algorithm

K. Janshi Lakshmi *, G. Sreenivasulu **
*-** Department of Electronics and Communication Engineering, Sri Venkateswara University College of Engineering, Sri Venkateswara University, Tirupati, Andhra Pradesh, India.
Periodicity:January - June'2021
DOI : https://doi.org/10.26634/jcs.10.1.18378

Abstract

Now-a-days, secured information transfer to others require security because the data might be stolen from hackers. To avoid these type of problems, are use Cryptography Secure Algorithms. Cryptography Algorithms play important role in network security. It is an Advanced Encryption Standard (AES) Algorithm. The AES is a Symmetric encryption using private key. This encryption process consists of blocks such as Key Expansion, Pre Round Operation, Add Round Key, Sub Bytes, Shift Rows and Mix Column. The Advanced encryption standard algorithm is using cryptographic secret keys-128 bits, 192 bits, and 256 bits to encryption, and decryption input data is 128 bits. This paper represents the survey of Cryptography Secure AES algorithm.

Keywords

Cryptography, AES, Symmetric, Private Key.

How to Cite this Article?

Lakshmi, K. J., and Sreenivasulu, G. (2021). A Review on FPGA Based Design of Advanced Encryption Standard (AES) Cryptography Secure Algorithm. i-manager's Journal on Communication Engineering and Systems, 10(1), 30-40. https://doi.org/10.26634/jcs.10.1.18378

References

[1]. Abhijith, P. S., Srivastava, M., Mishra, A., Goswami, M., & Singh, B. R. (2013, March). High performance hardware implementation of AES using minimal resources. In 2013, International Conference on Intelligent Systems and Signal Processing (ISSP) (pp. 338-343). IEEE. https://doi.org/10.110 9/ISSP.2013.6526931
[2]. Andriani, R., Wijayanti, S. E., & Wibowo, F. W. (2018, November). Comparision Of AES 128, 192 And 256 Bit Algorithm For Encryption And Description File. In 2018, 3rd International Conference on Information Technology, Information System and Electrical Engineering (ICITISEE) (pp. 120-124). IEEE. https://doi.org/10.1109/ICITISEE.2018. 8720983
[3]. Balupala, H. K., Rahul, K., & Yachareni, S. (2021, April). Galois Field Arithmetic Operations using Xilinx FPGAs in Cryptography. In 2021, IEEE International IoT, Electronics and Mechatronics Conference (IEMTRONICS) (pp. 1-6). IEEE. https://doi.org/10.1109/IEMTRONICS52119.2021.942 2551
[4]. Chauhan, Y. S., & Sasamal, T. N. (2019, July). Enhancing Security of AES Using Key Dependent Dynamic Sbox. In 2019, International Conference on Communication and Electronics Systems (ICCES) (pp. 468-473). IEEE. https:// doi.org/10.1109/ICCES45898.2019.9002543
[5]. Chawla, S. S., & Goel, N. (2015). FPGA implementation of an 8-bit AES architecture: A rolled and masked S-Box approach. Annual IEEE India Conference (INDICON), 1-6. https://doi.org/10.1109/INDICON.2015.7443814
[6]. Daemen, J., & Rijmen, V. (1999). AES Proposal: Rijndael. AES Algorithm Submission. Retrieved from http://csrc.nist. gov/encryption/aes/Rijndael.pdf
[7]. Davis, C., Muthineni, A., & John, E. (2019, August). Low- Power Advanced Encryption Standard for Implantable Cardiac Devices. In 2019, IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) (pp. 41-44). IEEE. https://doi.org/10.1109/MWSCAS.2019.8884946
[8]. Equihua, C., Anides, E., García, J. L., Vázquez, E., Sánchez, G., Avalos, J. G., & Sánchez, G. (2021). A lowcost and highly compact FPGA-based encryption/ decryption architecture for AES algorithm. IEEE Latin America Transactions, 19(9), 1443-1450. https://doi.org/ 10.1109/TLA.2021.9468436
[9]. Equihua, C., Anides, E., García, J. L., Vázquez, E., Sánchez, G., Avalos, J. G., & Sánchez, G. (2021). A lowcost and highly compact FPGA-based encryption/ decryption architecture for AES algorithm. IEEE Latin America Transactions, 19(9), 1443-1450. https://doi.org/ 10.1109/TLA.2021.9468436
[10]. FIPS PUB 197. (2001). Advanced Encryption Standard (AES). Retrieved from https://nvlpubs.nist.gov/nistpubs/fips/ nist.fips.197.pdf
[11]. Gaded, S. V., & Deshpande, A. (2019, June). Composite field arithematic based S-Box for AES algorithm. In 2019, 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA) (pp. 1209-1213). IEEE. https://doi.org/10.1109/ICECA.2019.88 21862
[12]. Good, T., & Benaissa, M. (2006). Very small FPGA application-specific instruction processor for AES. IEEE Transactions on Circuits and Systems I: Regular Papers, 53(7), 1477-1486. https://doi.org/10.1109/TCSI.2006.8751 79
[13]. Hasamnis, M. A., & Limaye, S. S. (2012, July). Design and implementation of Rijindael's encryption algorithm with hardware/software co-design using NIOS II processor . In 2012, 7th IEEE Conference on Industrial Electronics and Applications (ICIEA) (pp. 1386-1389). IEEE. https://doi.org/ 10.1109/ICIEA.2012.6360939
[14]. Huddar, S. R., Rupanagudi, S. R., Ravi, R., Yadav, S., & Jain, S. (2013, August). Novel architecture for inverse mix columns for AES using ancient Vedic Mathematics on FPGA. In 2013, International Conference on Advances in Computing, Communications and Informatics (ICACCI) (pp. 1924-1929). IEEE. https://ieeexplore.ieee.org/xpl/ dwnldReferences?arnumber=6637476
[15]. Jindal, P., Kaushik, A., & Kumar, K. (2020, July). Design and Implementation of Advanced Encryption Standard Algorithm on 7th Series Field Programmable Gate Array. In 2020, th7 International Conference on Smart Structures and Systems (ICSSS) (pp. 1-3). IEEE. https://doi.org/10.1109/ ICSSS49621.2020.9202114
[16]. Kaur, J., Lamba, S., & Saini, P. (2021, March). Advanced Encryption Standard: Attacks and Current Research Trends. In 2021, International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE) (pp. 112-116). IEEE. https://doi.org/ 10.1109/ICACITE51222.2021.9404716
[17]. Li, H., & Friggstad, Z. (2005, May). An efficient architecture for the AES mix columns operation. In 2005, IEEE International Symposium on Circuits and Systems (pp. 4637-4640). IEEE. https://doi.org/10.1109/ISCAS.2005.146 5666
[18]. Mohan, G., & Rambabu, K. (2014). An efficient FPGA implementation of the advanced encryption standard algorithm. International Journal for Scientific Research & Development (IJSRD), 2(07), 413-417.
[19]. NIST. (1999). Data Encryption Standard (DES). National Technical Information Service, Sprinfgield, VA.
[20]. Peng, G., & Zhu, S. (2021, March). FPGA Implementation of AES Encryption Optimization Algorithm. In 2021, International Conference on Intelligent Transportation, Big Data & Smart City (ICITBS) (pp. 650-653). IEEE. https://doi.org/10.1109/ICITBS53129.2021.00165
[21]. Rao, M. R., & Sharma, R. K. (2017, July). FPGA th implementation of combined AES-128. In 2017, 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT) (pp. 1-6). IEEE. https://doi.org/10.1109/ICCCNT.2017.8203966
[22]. Shashidhar, R., Mahalingaswamy, A. M., Kumar, P., & Roopa, M. (2018, December). Design of High Speed AES System for Efficient Data Encryption and Decryption System using FPGA. In 2018, International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT) (pp. 1279-1282). IEEE. https://doi.org/10.1109/ICEECCOT43722.2018.9001 535
[23]. Shreenivas Pai, N., Raghuram, S., Chennakrishna, M., & Karthik, A. V. (2017). Logic optimization of AES S-Box. In International Conference on Automatic Control and Dynamic Optimization Techniques, ICACDOT (Vol. 2016, pp. 1042-1046).
[24]. Srilaya, S., & Velampalli, S. (2018, May). Performance evaluation for des and AES algorithms-an comprehensive overview. In 2018, 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT) (pp. 1264-1270). IEEE. https://doi.org/ 10.1109/RTEICT42901.2018.9012536
[25]. Srinivas, N. S., & , M. D. (2016, March). FPGA based hardware implementation of AES Rijndael algorithm for Encryption and Decryption. In 2016, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) (pp. 1769-1776). IEEE. https://doi.org/ 10.1109/ICEEOT.2016.7754990
[26]. Stallings. W. (2006). Cryptography and Network Security-Principles and Practice (5th Edition). Prentice Hall, Pearson.
[27]. Ueno, R., Morioka, S., Miura, N., Matsuda, K., Nagata, M., Bhasin, S., ... & Homma, N. (2019). High throughput/ gate AES hardware architectures based on datapath compression. IEEE Transactions on Computers, 69(4), 534- 548. https://doi.org/10.1109/TC.2019.2957355
[28]. Wang, W., Chen, J., & Xu, F. (2012, May). An implementation of AES algorithm Based on FPGA. In 2012, 9th International Conference on Fuzzy Systems and Knowledge Discovery (pp. 1615-1617). IEEE. https://doi. org/10.1109/FSKD.2012.6233811
[29]. Yendamury, G., & Mohankumar, N. (2021, April). Defense in Depth approach on AES Cryptographic Decryption core to Enhance Reliability. In 2021, IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS) (pp. 1-7). IEEE. https://doi.org/ 10.1109/IEMTRONICS52119.2021.9422567
[30]. Yuan, Y., Yang, Y., Wu, L., & Zhang, X. (2018, June). A high performance encryption system based on AES algorithm with novel hardware implementation. In 2018, IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC) (pp. 1-2). IEEE. https://doi.org/ 10.1109/RTEICT42901.2018.9012536
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