An adder is the basic computational circuit in Very Large Scale Integration (VLSI) digital design. To improve the design metrics of an adder, Approximate Adders (AAs) have been proposed. These adders have been applied and analyzed on 8x8 Dadda Multipliers (DMs). The design metrics of proposed AAs, Approximate Dadda Multipliers (ADMs) are synthesized in Cadence Register-Transfer Level (RTL) compiler and compares the design metrics with three different technology nodes. The HDL synthesis results shows that the delay to the output of the proposed 8-tap filter gains an improvement over the conventional method. The implementation is done using Verilog HDL. Simulation and synthesis are done with the Xilinx ISE tool.