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Simulation of Cascaded Gate-Based Ternary Content-Addressable Memory

Pavithra S.*, P. Deepa **

*-** Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, Tamil Nadu, India.

Periodicity:July - December'2020
DOI : https://doi.org/10.26634/jcir.8.2.18087

Abstract

This paper presents a design for Gate-based ternary content-addressable memory (G-TCAM), utilizing G-AETCAM cells, which yields the location of given input information. The G-AETCAM cells utilizes flip-flop as memory component and control rationale hardware comprising of rationale entryways. One G-AETCAM cell encodes the input and put away the output into one encoded bit which brings about a match-line subsequent to passing from the input. G-AETCAM architecture is area efficient in terms of transistor count and speed of operations is high than the available TCAM architectures. The cascaded G-AETCAM cells are divided as banks, by considering each row as single bank of whole memory. The decoder logic used for memory design is modified by using reversible logic gate technique. Here, HL gate has been used instead of Line Decoder

Keywords

CAM Memory, TCAM Memory, G-AETCAM Memory, Bank Selection, Power and Speed of Memory, Reversible Logic Gate, HL Gate.

How to Cite this Article?

Pavithra, S., and Deepa, P. (2020). Simulation of Cascaded Gate-Based Ternary Content-Addressable Memory. i-manager's Journal on Circuits and Systems, 8(2), 29-35. https://doi.org/10.26634/jcir.8.2.18087

References

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