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Optimization of Metal Interconnects in I/O Cells and Banks to Improve Robustness of ESD Protection Network in 16 nm FinFet Technology for Flip Chip and Wire Bond Applications

Oleg Semenov *, Ekaterina Dumalkina **

*-** NXP Semiconductors, Moscow, Russia.

Periodicity:July - December'2020
DOI : https://doi.org/10.26634/jcir.8.2.18079

Abstract

As IC technologies move forward into sub-16 nm domains, ESD protection design is rapidly becoming a big IC design challenge. Interconnects inherently forms part of any ESD protection network. Without careful and quantitative design of metal interconnects, it would not be possible to achieve robust whole-chip ESD protection circuit. Usually, a failed metal interconnect forms an connection. ESD stress results in the permanent change in the interconnects resistance and the electro migration lifetime reduction. To optimize the interconnects of ESD devices and networks, the EDA software should be used. It performs electrical simulation and is capable to analyzing the large complex metal interconnects in the standalone cells and small blocks. In this paper, we analyze and optimize the metal interconnects in standalone I/O cell and small I/O bank with respect to CDM ESD stress using simulations in the industrial EDA tool. The layouts of these cells were implemented in 16 nm FinFet technology with 9M metal stack suitable for flip chip and wire bond applications. Both GDS and CCI based flows were applied. The effect of the ESD current distribution at the contact area of the anode and cathode and its accuracy of were investigated. Finally, the recommendations for interconnects (metal frame) optimization in the I/O cells with respect to CDM ESD stress were elaborated.

Keywords

Electrostatic Discharge (ESD), I/O Cell, Metal Interconnects, EDA Software.

How to Cite this Article?

Semenov, O., and Dumalkina, E. (2020). Optimization of Metal Interconnects in I/O Cells and Banks to Improve Robustness of ESD Protection Network in 16 nm FinFet Technology for Flip Chip and Wire Bond Applications. i-manager's Journal on Circuits and Systems, 8(2), 1-9. https://doi.org/10.26634/jcir.8.2.18079

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