Evolutionary Approach of Adiabatic Logic Design on Low Power Solution –A Robust Survey

A. Kishore Kumar*, D. Somasundareswari**, V.Duraisamy***, ****
* Dean, Electrical Sciences, Adithya Institute of Technology, Coimbatore, India.
*** Professor & Principal, Hindustan College of Engineering & Technology, Coimbatore, India.
**** Assistant Professor, ECE Department, Coimbatore Institute of Technology, Coimbatore, India.
Periodicity:February - April'2012
DOI : https://doi.org/10.26634/jcs.1.2.1775

Abstract

Adiabatic Logic styles in low power VLSI design have been examined for many years to achieve predictable low power design success.  In this paper, we present a comprehensive literature review pertaining to the state-of-the-art issues in adiabatic logic designs and also focus on primary developments in this field that have taken place in the low power design. Various research papers and application notes have been referred to, for clear understanding of adiabatic logic designs on low power solutions. Major focus of this paper is to identify the gaps of the adiabatic logic designs and to narrow down the problems and requirements for its practical usage in semiconductor industries. Enough designs and methods have been proposed over last few decades, but the implementation of this logic, triggers the designer in various open points, which restricts further stems. This paper highlights the major open points and gives the solution for further design requirement to implement the adiabatic logic in semiconductor industries.

Keywords

Low power, adiabatic logic, asynchronous, semiconductor industry, Moore’s law.

How to Cite this Article?

Kumar, A. K., Somasundareswari, D., Duraisamy, V. and Pradeepa, T. S. (2012). Evolutionary Approach Of Adiabatic Logic Design On Low Power Solution - A Robust Survey. i-manager’s Journal on Communication Engineering and Systems, 1(2), 36-49. https://doi.org/10.26634/jcs.1.2.1775

References

[1]. Cheryl Ajluni, (2009). “Existing Circuit Styles Shed Light on Low-Power Design”, Low Power Engineering Community (www.chipdesignmag.com).
[2]. J.G. Koller and W.C. Athas, (1992). “Adiabatic Switching, Low Energy Computing, and the Physics of Storing and Erasing Information”, Proceedings of the 2nd Workshop on Physics and Computation (PhysComp'92), pp. 267-270.
[3]. Gary K. Yeap, (1998). “Practical low power digital VLSI design” Springer.
[4]. A. Kishore Kumar, D. Somasundareswari, V. Duraisamy and M. Pradeepkumar (2010). “Low Power Multiplier Design Using Complementary Pass-Transistor synchronous Adiabatic Logic” International Journal on Computer Science and Engineering, Vol. 02, No. 07, 2291-2297.
[5]. Peiyi Zhao Zhongfeng Wang, (2009). “Low power design of vlsi circuits and systems”, IEEE 8th International Conference on ASIC, pages 17 – 20.
[6]. Michael A. Fury, (2012). “Reports on SEMI's Industry Strategy Symposium (ISS) 2012”, (www.electroiq.com)
[7]. R.T. Hinman and M.F. Schlecht, (1993). “Recovered Energy Logic – A Highly Efficient Alternative to Today's Logic Circuits”, Record of the 24th Annual IEEE Power Electronics Specialists Conference (PESC'93), pp. 17-26.
[8]. Younis, Saed G., and T.F. Knight Jnr (1994). “Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic”, International Workshop on Low Power Design, pages 177-182.
[9]. A. Kramer, J.S. Denker, S.C. Avery, A.G. Dickinson and T. R. Wik, (1994). “Adiabatic Computing with the 2n-2n2d Logic Family”, Symposium on VLSI Circuits – Digest of Technical Papers, pp. 25-26.
[10]. A.G. Dickinson and J.S. Denker, (1994). “Adiabatic Dynamic Logic”, Proceedings of the IEEE Custom Integrated Circuits Conference (CICC'94), pages 282-285.
[11]. W.Y. Wang and K.T. Lau, (1995). “Adiabatic pseudodomino logic”, Electronics Letters, 31(23): pages 1982- 1983.
[12]. D. Maksimovic, V.G. Oklobdzija, B. Nikolic and K.W. Current, (1997). “Clocked CMOS Adiabatic Logic with Integrated Single-Phase Power-Clock Supply: Experimental Results”, Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED'97), pages 323-327.
[13]. Yong Moon and Deog-Kyoon Jeong, (1996). “An efficient charge recovery logic circuit”, IEEE Journal of Solid-State Circuits, 31(4):514-522.
[14]. A. Kramer, J.S. Denker, B. Flower and J. Moroney, (1995). “2nd Order adiabatic computation with 2n-2p and 2n-2n2p logic circuits”, Proceedings of IEEE Symposium Low Power Design (ISLPD'95), pp. 191-196.
[15]. D. Mateo and A. Rubio, (1996). “Quasi-adiabatic ternary CMOS logic”, Electronics Letters, 32(2): 99 – 101.
[16]. A. Vetuli, S.D. Pascoli and L.M. Reyneri, (1996). “Positive feedback in adiabatic logic”, Electronics Letters, 32(20):1867-1869.
[17]. V.K. De and J.D. Meindl, (1996a). “Complementary Adiabatic and Fully Adiabatic MOS Logic Families for Gigascale Integration”, 43rd IEEE International Solid State Circuits Conference – Digest of Technical Papers, pages 300-301 and 462.
[18]. V.K. De and J.D. Meindl, (1996b). “Opportunities for non-dissipative computation [adiabatic logic]”, Proceedings of 9th annual IEEE ASIC Conference and Exhibit, pages 297-300.
[19]. V.G. Oklobdzija, D. Maksimovic and Fengcheng Lin, (1997). “Pass-Transistor Adiabatic Logic Using Single Power- Clock Supply”, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 44(10):842-846.
[20]. Y. Ye, K. Roy and G.I. Stamoulis, (1997). “Quasi-Static Energy Recovery Logic and Supply-Clock Generation Circuits”, Proceedings of the 1997 International Symposium on Low Power Electronics and Design (ISLPED'97), pages 96-99.
[21]. K.T. Lau and F. Liu, (1997). “Improved adiabatic pseudo-domino logic family ”, Electronics Letters, 33(25):2113-2114.
[22]. K. Kwon and S.I. Chae, (1998). “Simple reversible energy recovery logic using NMOS switch networks with cross-coupled PMOS pair ”, Electronics Letters, 34(23):2215-2216.
[23]. Chun-Keung Lo and Philip C. H. Chan, (1998). “Design of Low Power Differential Logic Using Adiabatic Switching Technique”, Proceedings of the International Symposium on Circuits and Systems (ISCAS'98), volume 2, pages II: 33-36.
[24]. F. Liu and K. T. Lau, (1998). “Pass-transistor adiabatic logic with NMOS pull-down configuration”, Electronics Letters, 34(8):739-741.
[25]. F. Liu and K.T. Lau, (1998). “Improved structure for efficient charge recovery logic”, Electronics Letters, 34(18):1731-1732.
[26]. S. Kim and M.C. Papaefthymiou, (1999). “Singlephase Source-Coupled Adiabatic Logic”, Proceedings of the 1999 International Symposium on Low Power Electronics and Design, pages 97-99.
[27]. Kazukiyo Takahashi and Mitsuru Mizunuma, (2000). “Adiabatic Dynamic CMOS Logic Circuit”, Electronics and Communications in Japan, part 2, 83(5):50-58.
[28]. Luo Jiajun, Li Xiaomin, Qiu Yulin and Chen Chaoshu (2001). “A new type of bootstrapped charge-recovery logic circuit”, Proceedings of 4th International Conference on ASIC, 21(9): 563 - 565.
[29]. D. Suvakovic and C. Salama, (2000). “Two phase nonoverlapping clock adiabatic differential cascode voltage switch logic”, IEEE International Solid-State Circuits Conference – Digest of Technical Papers (ISSCC'2000), pages 364-365.
[30]. L. Varga, F. Kovacs and G. Hosszu, (2001a). “An Efficient Adiabatic Charge- Recovery Logic”, Proceedings of the IEEE South East Conference, pages 17-20.
[31]. L. Varga, F. Kovacs and G. Hosszu, (2001b). “An Improved Pass-Gate Adiabatic Logic”, Proceedings 14th Annual International ASIC/SOC Conference, pp.208-211.
[32]. R. C. Chang, P.C. Hung and I.H. Wang, (2002). “Complementary pass transistor energy recovery logic for low-power applications”, IEE Proceedings on Computers and Digital Techniques, 149(4):146-151.
[33]. Hu Jianping, Cen Lizhang and Liu Xiao, (2003). “A new type of low-power adiabatic circuit with complementary pass-transistor logic”, Proceedings of 5th International Conference on ASIC (ASIC'03), volume 2, pages II: 1235-1238.
[34]. B.W. Widjaja and K.T. Lau, (2003). “Improved Adiabatic Pseudo Domino Logic 2”, Electronics Letters, 39(16):1167-1169.
[35]. J. Fischer, E. Amirante, A. Bargagli-Stoffi and D. Schmitt-Landsiedel, (2004). “Improving the positive feedback adiabatic logic family”, Advances in Radio Science, vol. 2, pp. 221–225.
[36]. Y. He, J. Tian, X. Tan and H. Min, (2006). “Quasi-static adiabatic logic 2N-2N2P2D family”, Electronics Letters, 42(16):905-906.
[37]. Shun Li, Feng Zhou, Chunhong Chen, Hua Chen and Yipin Wu, (2007). “Quasi-Static Energy Recovery Logic with Single Power-Clock Supply”, Proceedings of International Symposium on Circuits and Systems (ISCAS 2007), pages 2124-2127.
[38]. Ponnusamy Vijayakumar, M. Shanthanalakshmi and Kandasamy Gunavathi, (2007a). “Optimizing CMOS Circuits for Performance Improvements Using Adiabatic Logic“, Information Technology Journal, 6(3):325-331.
[39]. Ponnusamy Vijayakumar and Kandasamy Gunavathi, (2007b). “Energy Efficient Charge Recovery for Positive Feedback Adiabatic Logic”, IETE Technical Review, 24(2):127-133.
[40]. C.P. Kumar, S.K. Tripathy and R. Tripathi, (2009). “High per formance sequential circuits with adiabatic complementary pass-transistor logic (ACPL)”, IEEE Region 10 Conference, pages 1 – 4 and 23-26.
[41]. N.S.S. Reddy, M. Satyam, K.L. Kishore, (2008). “Cascadable adiabatic logic circuits for low-power applications”, IET Circuits, Devices & Systems, Volume: 2, Issue: 6, pages 518 – 526.
[42]. Gong, C.Y.A., Muh-Tian Shiue, Ci-Tong Hong, & Kai- Wen Yao, (2008). “Analysis and Design of an Efficient Irreversible Energy Recovery Logic in 0.18- um CMOS”, IEEE Transactions on Circuits and Systems I, Vol. 55, Issue: 9, pages: 2595 – 2607.
[43]. David J. Willingham and Izzet Kale, (2011). “A Ternary Adiabatic Logic (TAL) implementation of a four-trit Full- Adder”, Proceedings of Norchip 2011, pages 1-4.
[44]. David J. Willingham and Izzet Kale, (2004). “Asynchronous, quasi- Adiabatic (Asynchrobatic) logic for low power very wide data width applications”, Proceedings of International Symposium on Circuits and Systems, volume 2, pages II: 257-260.
[45]. David J. Willingham and Izzet Kale, (2008a). “An Asynchrobatic, Radix-four, Carry Look-ahead Adder”, Proceedings of PhD Research in Microelectronics and Electronics, pages 105-108.
[46]. David J. Willingham and Izzet Kale, (2008b). “Using Positive Feedback Adiabatic Logic to implement Reversible Toffoli Gates”, Proceedings of Norchip 2008, pages 5-8.
[47]. David J. Willingham and Izzet Kale, (2008c). “A system for calculating the Greatest Common Denominator implemented using Asynchrobatic Logic”, Proceedings of Norchip 2008, pages 194-197.
[48]. Muhammad Arsalan and Maitham Shams, (2007). “Asynchronous Adiabatic Logic”, IEEE International Symposium on Circuits and Systems, pages. 3720- 3723.
[49]. A. KishoreKumar, D. Somasundareswari, V. Duraisamy and T. Shunbaga Pradeepa (2011). “Design of Low Power Full Adder Using Asynchronous Adiabatic Logic”, European Journal of Scientific Research, Vol.63, No.3, pages 358- 367.
[50]. Jianping Hu, Binbin Liu, Dong Zhou, and Xiaoyan Luo, (2009). “Low-Power Adiabatic Pins for Driving Chip Pads”, IEEE Computer Society, pages 408-412.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.