Low Power Reconfigurable VLSI Architecture For FIR Filters

S. Karthick*, Nirmal Kumar**, S.Valarmathy***
*-**-*** Department of Electronics & Communication Engineering, Bannari Amman Institute of Technology, Sathyamangalam, India.
Periodicity:March - May'2012
DOI : https://doi.org/10.26634/jele.2.3.1766


Reconfigurability and low complexity are the two key requirements of finite impulse response (FIR) filters. Two new efficient reconfigurable architectures namely constant shift method (CSM) and programmable shift method (PSM) of low complexity are used for design of higher order finite impulse response (FIR) filters. The FIR filter architecture is capable of operating for different wordlength filter coefficients without any overhead in hardware circuitry. The CSM results in higher speed whereas the PSM results in lower area. These methods are based on the binary common subexpression elimination (BCSE) algorithm using canonical signed digit (CSD) representation of coefficients. The CSD representation is widely used in implementing multiple constant multiplication because it guarantees the least number of additions for a given constant multiplication. Hence the CSM architecture is used for high speed applications and the PSM architecture is used in applications where area and power have to be minimized. The experimental results are synthesized and major parameters like area , delay, power are compared for both CSM and PSM architecture using Xilinx ISE 8.1tool.


FIR Filters- CSM-PSM, Tanner EDA.

How to Cite this Article?

S. Karthick, R.Nirmal Kumar and S.Valarmathy (2012). Low Power Reconfigurable VLSI Architecture For FIR Filters. i-manager’s Journal on Electronics Engineering, 2(3), 22-29. https://doi.org/10.26634/jele.2.3.1766


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