Most modern digital circuits use synchronous design techniques. With the increase in operation frequency, the requirement for the delay stability is very strict. But even when design is completed, circuit parameters such as capacitance, resistance, as well as transistor's behaviour can only be modelled with limited accuracy, and these characteristics can vary with PVT (Process, Voltage, Temperature). The complexity and interactions among these factors make exact timing design of digital circuit an increasingly difficult task, and even with proper design, some percentage of manufactured circuits will fail to meet timing specification. We propose a method for fine-tuning circuit timing and duty cycle adjustment after fabrication. It allows correcting post-fabrication timing errors.