References
[1]. Roy, K. et al. (2003). Proceeding of IEEE, Feb.
[2]. DAC' (2004). Proceedings of the 41 Annual Design Automation Conference, ACM NEW York, NY, USA.
[3]. Taur, Y., & Ning, T.H. (1998). Fundamentals of Modern
VLSI Devices, Cambridge University Press.
[4]. Seok, M., Sylvester, D., & Blaauw, D. (2008). The
Phoenix Processor: A 30pW Platform for Sensor
Applications. Symp. VLSI Circuits, pp.188–189.
[5]. Ickes, N., Bhardwaj, M., Awang, & Chandrakasan, A.
P., (2008). A 10-pJ/instruction, 4-MIPS Micropower DSP for
Sensor Applications. Proc. ASSCC, pp.289–292.
[6]. Zhai, B., Blaauw, D., Sylvester, D., and Lautner, K.
(2004). Theoretical And practical limits of dynamic
st Voltage Scaling. Proc. 41 Design Automation Conf. Jun.
pp. 868–873.
[7]. Wei, L., Chen, Z., and Roy, K. (1999). Design and
Optimization of Dual Threshold Circuits for Low Voltage,
Low Power Applications. IEEE Transaction on VLSI Systems,
Vol. 17, No. 1, pp. 16-24.
[8]. Karnik, T., Borkar, S., and De, D. (2002). Sub-90 nm
Technologies Challenges and Opportunities for CAD,”
ACM/IEEE ICCAD, pp. 203-206.
[9]. Ye, Y., Borkar, S. and De, S., (1998). A New Technique
for Standby Leakage Reduction in High-Performance
Circuits. Symposium on VLSI Circuits, pp. 40-41.
[10]. Johnson, M. C., Somasekhar, D. and Roy, K., (1999).
Models and Algorithms for Bounds on Leakagein CMOS
Circuits. IEEE Trans. On CAD, Vol. 18, pp. 714-725.
[11]. Mutoh, S. S., Douseki, T., Matsuya, Y., Aoki, T.,
Sigematsu, S., and Yamada, J. (1995). IEEE J. Solid-State
Circuits, Vol. 30, pp. 847-854.
[12]. Kao, J., Chandrakasan, A., and Antoniadis, D.,
(1997). Transistor Sizing Issues and Tool for Multi-Threshold
CMOS Technology. Design Automation Conf., pp. 409-
414.
[13]. Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T.,
Yoshioka, Suzuki, K., Sano, F., Norishima, M., Murota, M.,
Kako, M., Kakumu, M. K. M., and Sakurai, T., (1996). A 0.9-
v, 150-mhz, 10-mw, 4 mm 2, 2-d discrete cosine transform
core processor with variable threshold-voltage (VT)
scheme. IEEE Journal of Solid-State Circuits, Vol. 31, pp.
1770-1779.
[14]. Keshavarzi, A. et al., (1999). Effectiveness of Reverse
Body Bias for Lowe Power CMOS Circuits. 8th NASA Symp.
VLSI Design, IEEE Press, Piscataway, NJ.
[15]. Tschanz, T. W., Narendra, S., Nair, R., De, D. (2003).
Effectiveness of adaptive supply voltage and body ... IEEE
Journal of Solid State Circuits, Vol. 38, Issue 5.
[16]. Kim, H. M. et al. (2002). ACM/IEEE DAC.
[17]. Nose, K. et al. (2001). IEEE Custom Integrated Circ.
Conf., 93.
[18]. Calhoun, B., & Chandrakasan, A.P. (2003). “Standby
Voltage Scaling for Reduced Power," CICC, PP. 639-642,
Orlando, FL.
[19]. Fuketa, H., Hashimoto, M., Mitsuyama, Y., and
Onoye, T. (2009). Trade-off Analysis Between Timing Error
Rate and Power Dissipation for Adaptive Speed Control
with Timing Error Prediction. ASP-DAC, pp. 266-271, NJ,
USA.
[20]. Das, S., Lee, S., Blaauw, D., Mudge, T., Nam Sung
Kim, Flautner, K. (2004). “Razor: Circuit- Level Correction
Of Timing Errors For Low-power Operation” Ieee
Computer Society Ieee.
[21]. Sato, Toshinori, Kunitake, Yuji, and Fukuoka, (2007).
A simple Flip-Flop Circuit for Typical Case Designs for DFM.
8th International Symposium on Quality Electronics Design,
PP. 539-544, San Jose, CA, ISQEB'07.
[22]. Sartori, J., and Kumar, R., (2009). Characterizing the
Voltage Scaling Limitations of Razor-based Designs.
Coordinated Science Laboratory, The University of Illinois
at Urbana-Champaign, Champaign, IL, Tech. Rep.
[23]. Blaauw, D., Das S. and Bull D., (2009). Razor II: In situ
error detection and Correction for PVT and SER tolerance.
IEEE Journal. Solid-State Circuits, Vol. 44, No. 1, pp. 32–48.
[24]. Chede, S., Kulat, K., and Thakare, R., (2010). A
Significance of VLSI Techniques for Low Power Real Time
Systems. IJCA, Vol. 1, pp. 22.
[25]. Pillai, P., and Shin, K.G. (2001). Real-Time Dynamic
Voltage Scaling for Low-Power Embedded Operating
Systems. Proc. SOSP, pp.89-102.
[26]. Fuket, H. et al., (2009). Adaptive performance
Compensation with In-Situ Timing Error prediction for Sub- threshold Circuits. CICC, PP.215 -218.
[27]. Fuketa, H., Hashimoto, M., Mitsuyama, Y., and
Onoye, T. (2011). Adaptive Performance Compensation
With In-Situ Timing Error Predictive Sensors for Sub-threshold
Circuits” Transaction on Very Large Scale Integration (VLSI)
Systems IEEE J., Vol. 9, pp. 1 - 11.
[28]. Samanta, R., Venkataraman, G., Shah, N., Hu, J.,
(2008). Elastic Timing Scheme for Energy-efficient and
Robust Performance”, ISQED, pp. 537-542.
[29]. Das S., Pant S., David R., Lee S. and Blaauw, D.
(2006). A self tuning DVS processor Using delay- error
detection and correction. IEEE J. Solid-State Circuits, Vol.
41, No. 4, pp. 792–804.
[30]. Kunitake, Y., Sato T., and Yasuura H. (2010). A Replacement Strategy for Canary Flip-Flops. PRDC, Vol.
4,pp. 227-228.
[31]. Benton H. Calhoun and Chandrakasan, (2004).
Standby Power Reduction Using Dynamic Voltage Scaling
and Canary Flip-Flop Structures. ISSC, Vol. 39,pp. 9.
[32]. Fuketa, H. Hashimoto, M. Mitsuyama, Y. Onoye, T.,
(2009). Adaptive Performance Compensation with In-Situ
Timing Error Prediction for Sub threshold Circuits” CICC, pp.
215-218.
[33]. Fuketa, H., Hashimoto, M,. Mitsuyama, Y., and
Onoye, T. (2011). Adaptive Performance Compensation
With In-Situ Timing Error Predictive Sensors for Sub threshold
Circuits. Transaction on Very Large Scale Integration (VLSI)
Systems IEEE J., Vol. 9, pp. 1 - 11.
