Arithmetic Compactors Design: Application to Mixed Signal Systems

Vadim Geurkov*, Lev Kirischian**
*-** Associate Professor, Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada.
Periodicity:February - April'2012
DOI : https://doi.org/10.26634/jes.1.1.1725

Abstract

Arithmetic error-control codes have been used to protect data transmission and processing. These codes are implemented through the use of appropriate encoding/decoding devices. An important part of these devices is a residue computing circuit, which has also found its application in mixed-signal systems testing. Arithmetic error-control codes originated to protect data transfers over binary channels; therefore the design methodology for residue computing circuits has been mostly oriented to the binary case. A non-binary design technique has only been known for the special type of compaction modulo. In this work, we consider a design technique for a multiple-bit arithmetic compaction circuit with an arbitrary compaction modulus. The compaction process causes some errors in the data being compacted to escape from detection. It is assumed that these data are distorted (the rate of distortion is known), which additionally increases the error escape rate. We show how to design compaction circuits that do not increase the error escape rate due to distortion.

Keywords

residue number systems, mixed-signal systems, built-in self-test, signature analysis

How to Cite this Article?

Geurkov,V., and Kirischian,L. (2012). Arithmetic Compactors Design: Application to Mixed Signal Systems. i-manager’s Journal on Embedded Systems. 1(1), 1-7. https://doi.org/10.26634/jes.1.1.1725

References

[1]. Actel Corporation. (2012). SmartFusion®: Intelligent Innovative Integration. No Compro- mises. Retrieved from http://www.actel. com/products/smartfusion/default.aspx
[2]. Collins, A. (2012). Xilinx Agile Mixed Signal Solutions. Retieved from http://www.xilinx.com/support/documentation/white_papers/wp392_Agile_Mixed_Signal.pdf
[3]. Dadaev, Y. (1981). Theory of Arithmetic Codes. Moscow: Radio i Sviaz (in Russian).
[4]. D'Antona, G., & Ferrero, A. (2006). Digital Signal Processing for Measurement Systems. Berlin: Springer Science + Business Media Inc.
[5]. Frohwerk, R. (1977). Signature Analysis: A New Digital Field Service Method. Hewlett Packard Journal, 28(9), 2-8.
[6]. Gookin, A. (1977). A fast reading high resolution voltmeter that calibrates itself automatically. Hewlett Packard Journal, 28(6), 2-10.
[7]. Kneller, V. (2003). Measurement, control and other processes: to the problem of knowledge systematization. Proceedings of the Seventinth IMEKO World Congress. Cavtat-Dubrovnik, Croatia, 1119-1124.
[8]. Lee, D., Yoo, K., Kim, K., Han, G., & Kang, S. (2004). Code-width testing-based compact ADC BIST circuit. IEEE Transactions on Circuits and Systems-II: Express briefs, 51(11), 603-606.
[9]. Mahoney, M. (1987). DSP-Based Testing of Analog and Mixed-Signal Circuits. Los Alamitos, CA: IEEE Computer Society Press.
[10]. Peterson, W., & Weldon, E. (1972). Error Correcting Codes. Cambridge, MA: The MIT Press.
[11]. Roberts, G. (1996). Metrics, Techniques and Recent Developments in Mixed-Signal Testing. Proceedings of the International Conference on Computer Aided Design, 1–8.
[12]. Starr, G., Qin, J., Dutton, B., Stroud, C., Dai, F., & Nelson, V. (2009). Automated Generation of Built-In Self- Test and Measurement Circuitry for Mixed-Signal Circuits and Systems. Proceedings of DFT '09: The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 11-19.
[13]. Stroude, C., Morton, J., Islam, T., & Alassaly, H. (2003). A Mixed-Signal Built-In Self-Test Approach for Analog Circuits. Proceedings of Southwest Symposium on Mixed-Signal Design. Las Vegas, NV, 196-201.
[14]. Vinnakota, B. (1998). Analog and Mixed-Signal Test. Upper Saddle River, NJ: Prentice Hall.
[15]. Wakerly, J. (1978). Error Detecting Codes, Self- Checking Circuits and Applications. New York, NY: Elsevier North-Holland.
[16]. Wang, Y.-S., Wang, J.-X., Lai F.-C., & Ye, Y.-Z. (2005). A low-cost BIST scheme for ADC testing. Proceedings of the Sixth International Conference on ASIC. Shanghai, China, 2, 665-668.
[17]. Wei, L., & Jia, L. (2008). An Apprach to Analong and Mixed-Signal BIST Based on Pseudo-Random Testing. Proceedings of the International Conference on Communications, Circuits and Systems, 1192–1195.
[18]. Wu, G., Rao, J., Ren A., & Ling, M. (2003). Implementation of a BIST scheme for ADC test. Proceedings of the Fifth International Conference on ASIC. Beijing, China, 2, 1128-1131.
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