Timing analysis is a very important part of the digital logic design procedure. As the complexity of the system increases the possibility of timing issues adversely affecting the system's functionality increases and the designer there after seeks use of computer aided software to assist in resolving such issues existing in the system. One major issue encountered in digital electronic system is that of static 1 hazards. A static-1 hazard is a possibility of a zero (0) glitch when a steady logic 1 output is expected. This project entails the development of a Graphical User Interface (GUI) for construction of combinational logic circuits, which allow for the identification and elimination of Static-1 Hazards. This tool will be used as a teaching aid. The user interface would be a menu-driven program written using Matlab to allow the user to easily identify and eliminate static-1 hazards from digital logic circuits and the algorithm selected to implement this feature was adopted from the consensus theorem. The learning is confined to a 3-input variable logic circuit design. The tool allows the user to design their own combinational circuits, then generate the corresponding truth table and Karnaugh map with its Sum-of-Product (SOP) expression. All existing static-1 hazards were illustrated on Karnaugh maps and the solution to eliminate the hazards by adding the consensus term to the SOP expression was demonstrated.