k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. The radix-2k fast Fourier transform algorithm is employed to achieve low power at the same time a radix-2 FFT algorithm reduced number of twiddle factor multiplication it reduces the area. This article describes a novel radix-24 multiple delay commutators called 4 - path feed forward FFT architecture utilizing the advantages of the radix-2 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more efficient in terms of hardware and higher throughput by implementing parallelism and multiple delay commutator. Combining benefits of both radix-2 algorithm and feed forward architecture, the proposed 4-path radix-24 FFT processor achieves the lowest hardware requirements for multipliers which is 20% lesser and power consumption which reduces more than 30% when compared with dual path radix-22 and radix-24 delay feedback FFT architecture. The entire FFT algorithms were implemented in Verilog hardware description language and synthesized with 90 nm Technology Libraries using Cadence RTL Compiler.

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Low Power and Area Efficient FFT Processor using Radix-24 Feed Forward Multipath Delay Commutator for Wireless Communication

C. Padma*, P. Jagadamba **, P. Ramana Reddy ***
*,*** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Ananthapuramu, Andhra Pradesh, India.
** Department of Electronics and Communication Engineering, Srikalahasthi Institute of Technology, Srikalahasti, Andhra Pradesh, India.
Periodicity:October - December'2019
DOI : https://doi.org/10.26634/jwcn.8.3.17115

Abstract

Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. The radix-2k fast Fourier transform algorithm is employed to achieve low power at the same time a radix-2 FFT algorithm reduced number of twiddle factor multiplication it reduces the area. This article describes a novel radix-24 multiple delay commutators called 4 - path feed forward FFT architecture utilizing the advantages of the radix-2 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more efficient in terms of hardware and higher throughput by implementing parallelism and multiple delay commutator. Combining benefits of both radix-2 algorithm and feed forward architecture, the proposed 4-path radix-24 FFT processor achieves the lowest hardware requirements for multipliers which is 20% lesser and power consumption which reduces more than 30% when compared with dual path radix-22 and radix-24 delay feedback FFT architecture. The entire FFT algorithms were implemented in Verilog hardware description language and synthesized with 90 nm Technology Libraries using Cadence RTL Compiler.

Keywords

 Fast Fourier Transform (FFT), Multiple Delay Commutator (MDC), Radix-2k FFT Algorithm

How to Cite this Article?

 Padma, C., Jagadamba, P., and Reddy, P. R. (2019). Low Power and Area Efficient FFT Processor using Radix-24 Feed Forward Multipath Delay Commutator for Wireless Communication. i-manager’s Journal on Wireless Communication Networks , 8(3), 10-17. https://doi.org/10.26634/jwcn.8.3.17115

References
[1]. Birdsong, J. B., & Rummelt, N. I. (2016, September). The hexagonal fast Fourier transform. In 2016, IEEE International Conference on Image Processing (ICIP) (pp. 1809-1812). IEEE. https://doi.org/10.1109/ICIP.2016.7532670
[2]. Chen, Y., & Chen, H. (2013, April). A efficient design of a real-time FFT architecture based on FPGA. In IET International Radar Conference Proceedings. The Institution of Engineering & Technology. https://doi.org/10. 1049/cp.2013.0368
[3]. Chen, Y., Lin, Y. W., Tsao, Y. C., & Lee, C. Y. (2008), A 2.4- Gsample/s DVFS FFT processor for MIMO OFDM communication systems. IEEE Journal of Solid-State Circuits, 43(5), 1260-1273. https://doi.org/10.1109/JSSC. 2008.920320
[4]. Chen, Y., Yi-zhuang, X., Chen, L., Chen, H., & Deng, Y. (2015, October), Design of a configurable fixed-point FFT processor. IET International Radar Conference, The Institution of Engineering & Technology. https://doi.org/10. 1049/cp.2015.1307
[5]. Heideman, M., Johnson, D., & Burrus, C. (1984), Gauss and the history of the fast Fourier transform. IEEE ASSP Magazine, 1(4), 14-21. https://doi.org/10.1109/MASSP. 1984.1162257
[6]. Jeon, D., Seok, M., Chakrabarti, C., Blaauw, D., & Sylvester, D. (2011), A super-pipelined energy efficient subthreshold 240 MS/s FFT core in 65 nm CMOS. IEEE Journal of Solid-State Circuits, 47(1), 23-34. https://doi.org/ 10.1109/JSSC.2011.2169311
[7]. Jiang, L. X., Liu, C. Y., & Zhang, P. (2012, October), A novel overall in-place in-order prime factor FFT algorithm. In 2012 5th International Congress on Image and Signal Processing (pp. 1500-1503). IEEE. https://doi.org/ 10.1109/CISP.2012.6469906
[8]. Mangaiyarkarasi, V., & Paul, C. K. C. (2014, July), Performance analysis between radix2, radix4, mixed radix4-2 and mixed radix8-2 FFT. In Second International Conference on Current Trends In Engineering and Technology-ICCTET 2014 (pp. 430-434). IEEE. https: //doi.org/10.1109/ICCTET.2014.6966332
[9]. Mittal, S., Khan, Z. A., & Srinivas, M. B. (2007, November), Area efficient high speed architecture of Bruun's FFT for software defined radio. In IEEE GLOBECOM 2007-IEEE Global Telecommunications Conference (pp. 3118-3122). IEEE. https://doi.org/10.1109/GLOCOM.2007. 590
[10]. Mohapatra, B. N., & Mohapatra, R. K. (2017, February), FFT and sparse FFT techniques and applications. In 2017 Fourteenth International Conference on Wireless and Optical Communications Networks (WOCN) (pp. 1-5). IEEE. https://doi.org/10.1109/WOCN. 2017.8065859
[11]. Mookherjee, S., DeBrunner, L., & DeBrunner, V. (2015, November), A low power radix-2 FFT accelerator for FPGA. In 2015 49th Asilomar Conference on Signals, Systems and Computers (pp. 447-451). IEEE. https://doi.org/10.1109/ ACSSC.2015.7421167
[12]. Padma, C., Jagadamba, P., & Reddy, P. R. (2018), A review on optimized FFT architectures for wireless communication system, Journal of Advanced Research in Dynamical and Control Systems, 10(14s), 1654-1662.
[13]. Padma, C., Jagadamba, P., & Reddy, P. R. (2020), Implementation of high Performance FFT architecture for DSP applications, International Journal of Advanced Science and Technology, 29(3s), 582-593.
[14]. Salehi, S. A., Amirfattahi, R., & Parhi, K. K. (2013), Pipelined architectures for real-valued FFT and Hermitiansymmetric IFFT with real datapaths. IEEE Transactions on Circuits and Systems II: Express Briefs, 60(8), 507-511. https://doi.org/10.1109/TCSII.2013.2268411
[15]. Wang, A., & Chandrakasan, A. (2005), A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE Journal of Solid-State Circuits, 40(1), 310-319. https://doi.org/10.1109/JSSC.2004.837945
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