k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. The radix-2k fast Fourier transform algorithm is employed to achieve low power at the same time a radix-2 FFT algorithm reduced number of twiddle factor multiplication it reduces the area. This article describes a novel radix-24 multiple delay commutators called 4 - path feed forward FFT architecture utilizing the advantages of the radix-2 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more efficient in terms of hardware and higher throughput by implementing parallelism and multiple delay commutator. Combining benefits of both radix-2 algorithm and feed forward architecture, the proposed 4-path radix-24 FFT processor achieves the lowest hardware requirements for multipliers which is 20% lesser and power consumption which reduces more than 30% when compared with dual path radix-22 and radix-24 delay feedback FFT architecture. The entire FFT algorithms were implemented in Verilog hardware description language and synthesized with 90 nm Technology Libraries using Cadence RTL Compiler.

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Low Power and Area Efficient FFT Processor using Radix-24 Feed Forward Multipath Delay Commutator for Wireless Communication

C. Padma*, P. Jagadamba **, P. Ramana Reddy ***
*,*** Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Ananthapuramu, Andhra Pradesh, India.
** Department of Electronics and Communication Engineering, Srikalahasthi Institute of Technology, Srikalahasti, Andhra Pradesh, India.
Periodicity:October - December'2019
DOI : https://doi.org/10.26634/jwcn.8.3.17115

Abstract

Radix-2k delay feed-back and radix-K delay commutator are the most well-known pipeline architecture for FFT design. The radix-2k fast Fourier transform algorithm is employed to achieve low power at the same time a radix-2 FFT algorithm reduced number of twiddle factor multiplication it reduces the area. This article describes a novel radix-24 multiple delay commutators called 4 - path feed forward FFT architecture utilizing the advantages of the radix-2 algorithm, such as simple butterflies and less memory requirement. Therefore, it is more efficient in terms of hardware and higher throughput by implementing parallelism and multiple delay commutator. Combining benefits of both radix-2 algorithm and feed forward architecture, the proposed 4-path radix-24 FFT processor achieves the lowest hardware requirements for multipliers which is 20% lesser and power consumption which reduces more than 30% when compared with dual path radix-22 and radix-24 delay feedback FFT architecture. The entire FFT algorithms were implemented in Verilog hardware description language and synthesized with 90 nm Technology Libraries using Cadence RTL Compiler.

Keywords

 Fast Fourier Transform (FFT), Multiple Delay Commutator (MDC), Radix-2k FFT Algorithm

How to Cite this Article?

 Padma, C., Jagadamba, P., and Reddy, P. R. (2019). Low Power and Area Efficient FFT Processor using Radix-24 Feed Forward Multipath Delay Commutator for Wireless Communication. i-manager’s Journal on Wireless Communication Networks , 8(3), 10-17. https://doi.org/10.26634/jwcn.8.3.17115

References
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