CMOS scaling relies on the device miniaturization and the interconnect dimensions to achieve high performance and curtails the escalating power-density. Since, multiplication algorithms and relevant high speed architectures extend significant contribution to the transient and dynamic power consumption of any system and thereby influence the total power consumption, multipliers of different bit-widths are deployed in signal and image Processing based VLSI applications ranging from processors to variety of application specific integrated circuits. On the other hand, Artificial Neural Networks (ANN) are well suitable for VLSI implementations because of their massive parallel structures comprised of processing Multiply Accumulate Carry (MAC) neuron elemental units. The proposed work focuses more on the design of variant bit Array Multiplier and Serial-Parallel Multiplier architectures targeting CMOS 130 nm technology. Both architectures are analyzed experimentally and relatively compared with rise-time, fall-time, power dissipation, delay parameters, etc.