Implementation of Power Reduction in CMOS Circuits

D. Suresh Kumar*, K. Rajasekhar **
* Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Jonnada, Andhra Pradesh, India.
** Department of Electronics and Communication Engineering, Baba institute of Technology & Sciences, Visakhapatnam, Andhra Pradesh, India.
Periodicity:September - November'2019
DOI : https://doi.org/10.26634/jcir.7.4.16832

Abstract

In recent trends, the industry and most researchers are focusing on the scale down of CMOS technologies to improve the speed and leakage power reduction in the circuits. These unsought leakage currents should be minimized for smooth functioning of the circuits. To develop such type of leakage-free CMOS circuits could be challenging. The main objective of the project is to address the issues over leakage power reductions, delay and efficiency. We present a circuit technique for mitigating MOSFET through controlling the voltage at source terminal of the MOSFET. In this paper we will present CMOS INVERTER, NAND, NOR, XOR using Lector technique. The simulation results are obtained with the aid of MENTOR GRAPHICS of 120 nm technology and also the comparisons of power dissipation by using with and without Lector techniques and with other techniques.

Keywords

Power Reduction, CMOS Technologies, Lector Techniques, Power Dissipation.

How to Cite this Article?

Kumar, D. S., and Rajasekhar, K. (2019). Implementation of Power Reduction in CMOS Circuits. i-manager's Journal on Circuits and Systems , 7(4), 20-26. https://doi.org/10.26634/jcir.7.4.16832

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