This article proposes new schemes for XOR/XNOR and concurrent XOR-XNOR functions. Due to low output capacitance and low short-circuit power dissipation, these circuits are well optimized in terms of power consumption and delay. Six novel hybrid 1-bit full adder (FA) circuits based on full-swing XOR/XNOR gates are also available. In terms of speed, power consumption, power delay product (PDP), driving ability, etc., each of these circuits has unique benefits. Extensive Mentor Graphics is used to study the performance of the designs. The simulation findings, which are based on a 130 nm CMOS process technology model, show that the suggested designs outperform previous FA solutions in terms of speed and power. To improve the PDP of the circuits, a novel transistor size strategy is provided. The approach employs a numerical computing particle swarm optimization algorithm to reach the target PDP value with fewer repetitions. The circuits are examined in terms of supply and threshold voltage fluctuations, output capacitance, input noise immunity, and transistor size.