130 Nm CMOS Technology based Baugh-Wooley and Wallace-Tree-Multiplier Architectures

Siripurapu Sridhar*, Hima Bindhu**, Paxani P.***
*-*** Lendi Institute of Engineering and Technology, Andhra Pradesh, India.
Periodicity:June - August'2019
DOI : https://doi.org/10.26634/jcir.7.3.16455

Abstract

The enhanced usage of multiplier circuits in various applications has prompted researchers to evolve high-speed and power optimized multiplier design architectures. Subsequently, power management optimizations as well as high speed designs are of greatest concern today, especially while working with digital signal processors, and other audio- video image processing circuits utilizing artificial neural networks. This work mainly focuses on providing efficient and optimized CMOS designs for 2-bit, 4-bit Wallace Tree Multiplier and Baugh-Wooley Multiplier architectures for applications in advanced filter designs comprised of simple to complex adders' circuits. The proposed architectures are verified experimentally using Mentor Graphics tools targeting the 130 nm technology design parameters. Design architectures are comparatively verified with relevant parameters like rise-time, fall-time, path delay, power dissipation, silicon area, etc. Both the architectures display few tradeoffs between power dissipation and delay parameters. Analysis with the implementation of proposed architectures for usage in Multipliers and Accumulate Carry (MAC) unit and other processing unit blocks are performed for further implementations.

Keywords

CMOS, Baugh- Wooley, Wallace Tree, Delay, Power Dissipation.

How to Cite this Article?

Sridar, S., Bindhu, H., and Paxani P. (2019). 130 Nm CMOS Technology based Baugh-Wooley and Wallace-Tree-Multiplier Architectures. i-manager's Journal on Circuits and Systems , 7(3), 17-25. https://doi.org/10.26634/jcir.7.3.16455

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