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Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL

Gopi Chand Naguboina*, T. Sravya**

* Department of Electronics and Communication Engineering, MVGR College of Engineering (A), Vizianagaram, Andhra Pradesh, India.

** Department of Electrical and Electronics Engineering, Lendi Institute of Engineering and Technology (A), Vizianagaram, Andhra Pradesh, India.

Periodicity:January - March'2019
DOI : https://doi.org/10.26634/jdp.7.1.16434

Abstract

This paper presents the design and implementation of Modified Booths encoding algorithm with enhanced speed. Multiplication is the most commonly used operation in every step of arithmetic. The speed of multiplier determines the speed of processor. So, there is a need for high speed multiplier. Adders play a dominant role in arithmetic addition of partial products. Increase in the speed of any arithmetic operation results in the increase of speed of overall operation of multiplier. So the main focus in this paper is to increase the speed of adder in turn increasing the speed of multiplication process. An algorithm is proposed using Modified Booths algorithm, Wallace tree structure, and Kogge-Stone adder design. MBE reduces the number of partial products and has least latency compared to other multiplier algorithms. Wallace tree structure increases the speed of accumulation of partial products. A Kogge-Stone adder design is used in the multiplier design, which yields to reduced delay and area. The proposed Modified Booth Multiplier design shows better performance compared to that of the conventional method using Kogge-Stone Adder and has advantages of reduced area overhead and critical path delay. The proposed design has been synthesized using Xilinx ISE 14.2 design tool using Verilog HDL.

Keywords

MBE Algorithm, Booth Encoder, Booth Decoder, Wallace Tree Multiplier, Kogge-Stone Adder.

How to Cite this Article?

Naguboina, G. C., & Sravya. T. (2019). Speed Enhancement of Modified Booths Encoding Algorithm Using Verilog HDL. i-manager’s Journal on Digital Signal Processing, 7(1), 20-27. https://doi.org/10.26634/jdp.7.1.16434

References

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