Design of Low Power High Speed Hybrid Adder

E. Anu Joe*, R. Manjith**
*-**Department of Electronics and Communication Engineering, Dr. Sivanthi Aditanar College of Engineering, Tiruchendur, Tamil Nadu, India.
Periodicity:July - December'2021
DOI : https://doi.org/10.26634/jdp.9.2.16284

Abstract

Adders are very important in Digital Signal Processing (DSP) for filter designing. It is profoundly accepted that the main processing unit of any device capable of carrying out computations is the Central Processing Unit (CPU). The most fundamental and integral part of the CPU is an Arithmetic and Logical Unit (ALU). Adders are the primary and indispensable component of ALU. There are various adders available in the literature such as Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), Carry Skip Adder (CSA), and Carry Increment Adder (CIA), etc. In this paper, a new hybrid adder is designed by combining the two significant adders such as the Carry Skip adder and the Carry increment adder. The hybrid adder has two main peripheral components namely RCA and Multiplexer. In this paper, the GDI technique is applied in both RCA and Multiplexer to design a new low-powerhigh-speed hybrid adder. Simulation is done using the Tanner EDA tool in 180nm technology and the results obtained show a significant improvement in power consumption and delay.

Keywords

Carry Increment Adder, Carry Skip Adder, Gate Diffusion Input (GDI) Technique, Hybrid Adder.

How to Cite this Article?

Joe, E. A., and Manjith, R. (2021). Design of Low Power High Speed Hybrid Adder. i-manager's Journal on Digital Signal Processing, 9(2), 8-14. https://doi.org/10.26634/jdp.9.2.16284

References

[5]. Kumar, P. K., & Srikanth, P. (2015). Design of Low Power High Speed Hybrid Full Adder. International Journal of Electronics & Communication Technology, 6(4), 14-19.
[7]. Sarangi, S., Swain, S., Dash, S., & Mohanta, M. (2014). VHDL Implementation of Arithmetic Logic Unit. International Journal of Engineering Research & Technology (IJERT), 3(4), 1214- 1221.
[8]. Sarma, R., & Raju, V. (2012). Design and performance analysis of hybrid adders for high speed arithmetic circuit. International Journal of VLSI Design & Communication Systems (VLSICS), 3(3), 1-12.
If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Single Article

North Americas,UK,
Middle East,Europe
India Rest of world
USD EUR INR USD-ROW
Pdf 35 35 200 20
Online 35 35 200 15
Pdf & Online 35 35 400 25

Options for accessing this content:
  • If you would like institutional access to this content, please recommend the title to your librarian.
    Library Recommendation Form
  • If you already have i-manager's user account: Login above and proceed to purchase the article.
  • New Users: Please register, then proceed to purchase the article.