Adders have always been area of continual research in VLSI for high speed data path design. There have been different architectures proposed with design metrics and both the structures are compared for the parameters of power consumption and delay. In the proposed architecture using True single phase clocked (TSPC), D-Latch for square root (SQRT) carry select look ahead adder is compared with Multi-Threshold complementary metal oxide semiconductor (CMOS) D-latch based design. The design shows power dissipation reduction about 56% than that of MTCMOS. Further the proposed architecture using Multi-Threshold TSPCD-Latch for SQRT carry select look ahead adder is compared with Multi-Threshold CMOSD-latch based designs, the design with TSPC shows the power delay product reduction about 11%. Further, the proposed design is compared with different existing carry select adder designs. Hence, the proposed structure which has small area and less power consumption is implemented for 8-bit adder to reduce the power consumption and delay.