i-manager Publications

Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency

Tripti Nirmalkar*, Deepti Kanoujia**, Kshitiz Varma***

* PG Scholar, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University,Chhattisgarh, India.

** Post Graduate, Department of Electronics and Communication Engineering, Sri Shankaracharya College of Engineering and Technology, Chhattisgarh, India.

*** Project Officer, Department of Electronics and Communication Engineering, Chhattisgarh Swami Vivekananda Technical University, Chhattisgarh, India.

Periodicity:June - August'2018
DOI : https://doi.org/10.26634/jcir.6.3.14877

Abstract

Research on reversible logic gates has become one of the interesting fields in the world of electronics. This has been proved to be one of the most reliable logics that originates its place in low power CMOS skills, Nano and optical calculation and many more. These broadsheet offers the comparison of different reversible logic gates in expressions of quantum cost, delay, transistor charge, and also implementation of one of the alterable logic gates, i.e. Peres gate in a conventional half adder with the help of an efficient algorithm. The work is performed in Xilinx using Verilog coding. The simulation result shows improved efficiency, low power, and low area consumption as related to the standard half adder. This half adder can be utilized in different applications, where circuit comprising of a conventional half adder can be replaced by Peres Half Adder (HAP).

Keywords

Reversible Logic Gates, Power Desolation, Garbage Output, Reversible Totaling, Quantum Cost, Transistor Cost, Half Adder (HA), Peres Gate Half Adder (HAP).

How to Cite this Article?

Nirmalkar, T., Kanoujia, D., and Varma, K. (2018). Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency. i-manager’s Journal on Circuits and Systems, 6(3), 36-42. https://doi.org/10.26634/jcir.6.3.14877

References

[1]. Babu, H. M. H., Islam, M. R., Chowdhury, A. R., & Chowdhury, S. M. A. (2003, September). Reversible logic synthesis for minimization of full-adder circuit. In Digital System Design, 2003. Proceedings. Euromicro Symposium on (pp. 50-54). IEEE.

[2]. Bennett, C. H. (1973). Logical reversibility of computation. IBM Journal of Research and Development, 17(6), 525-532.

[3]. Feynman, R. (1985). Quantum Mechanical Computers, Ocular Newsflash. 11-20.

[4]. Garipelly, R., Kiran, P. M., & Kumar, A. S. (2013). A review on reversible logic gates and their implementation. International Journal of Emerging Technology and Advanced Engineering, 3(3), 417-423.

[5]. Gupta, P., Agrawal, A., & Jha, N. K. (2006). An algorithm for synthesis of reversible logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(11), 2317-2330.

[6]. Hari, S. K. S., Shroff, S., Mahammad, N., and Kamakoti, V. (2006). Efficient building blocks for reversible sequential circuit design. In Proc. The 49^th IEEE Intl. Midwest Symposium on Circuits and Systems (pp. 437- 441).

[7]. Kanth, B. R., Krishna, B. M., Sridhar, M., & Swaroop, V. S. (2012). A distinguish between reversible and conventional logic gates.

[8]. Landauer, R. (1961). Irreversibility and heat generation in the computing process. IBM Journal of Research and Development, 5(3), 183-191.

[9]. Mamataj, S., Saha, D., & Banu, N. (2014). A review of reversible gates and its application in logic design. American Journal of Engineering Research, 3(4), 151- 161.

[10]. Maslov, D., & Dueck, G. W. (2004). Reversible cascades with minimal garbage. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(11), 1497-1509.

[11]. Peres, A. (1985). Reversible logic and quantum computers. Physical Review A, 32(6), 3266-3276.

[12]. Rajmohan, V., & Ranganathan, V. (2011, April). Design of counters using reversible logic. In Electronics Computer Technology (ICECT), 2011 3^rd International Conference on (Vol. 5, pp. 138-142). IEEE.

[13]. Thapliyal, H., & Ranganathan, N. (2009, May). Design of efficient reversible binary subtractors based on a new reversible gate. In Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate, IEEE.

[14]. Thapliyal, H., & Ranganathan, N. (2010a). Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM Journal on Emerging Technologies in Computing Systems (JETC), 6(4), 14.

[15]. Thapliyal, H., & Ranganathan, N. (2010b). Reversible logic-based concurrently testable latches for molecular QCA. IEEE Transactions on Nanotechnology, 9(1), 62-69.

[16]. Thapliyal, H., & Ranganathan, N. (2010c, January). Design of reversible latches optimized for quantum cost, delay and garbage outputs. In VLSI Design, 2010. VLSID'10. 23^rd International Conference on (pp. 235-240). IEEE.

[17]. Thapliyal, H., & Vinod, A. P. (2007, May). Design of reversible sequential elements with feasibility of transistor implementation. In Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on (pp. 625-628). IEEE.

[18]. Yelekar, P. R., & Chiwande, S. S. (2011, November). Introduction to reversible logic gates & its application. In 2^nd National Conference on Information and Communication Technology (pp. 5-9).

Implementation of Reversible Logic Gate (Peres Gate) to Design a Half Adder for Low Power with Reduced Area and Improved Efficiency

Abstract

Keywords

How to Cite this Article?

References

If you have access to this article please login to view the article or kindly login to purchase the article

Purchase Instant Access

Options for accessing this content:

	North Americas,UK, Middle East,Europe		India	Rest of world
	USD	EUR	INR	USD-ROW
Pdf	35	35	200	20
Online	35	35	200	15
Pdf & Online	35	35	400	25