i-manager Publications

Design and Verification of 16-Bit RISC Processor using SystemVerilog

S. M. Bhagat*, S. U. Bhandari**

* PG Scholar, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

** Professor, Department of Electronic and Telecommunication from Pimpri Chinchwad College of Engineering, Pune, Maharashtra, India.

Periodicity:September - November'2018
DOI : https://doi.org/10.26634/jcir.6.4.14864

Abstract

The regularly increasing complexity and size of the designs faces various issues with traditional verification methods. To address this issue a reuse-oriented, verification methodology should be adopted which is built on the rich semantic support of a standard language. This paper presents a design of a 16 bit RISC processor with 15 instructions. The design is described in each module and the performance of the design is also presented in convenient manner. Although the design cycle takes time, but more time is required for verification. To perform verification process, verification environment is built for few modules of this RISC processor using SystemVerilog. Among various verification methodologies here a simple approach of verification is presented.

Keywords

RISC, Von-Neumann Architecture, Systemverilog, Reuse-Oriented

How to Cite this Article?

Bhagat, S. M., Bhandari, S. U. (2018). Design and Verification of 16-Bit RISC Processor using System Verilog, i-manager's Journal on Circuits and Systems, 6(4), 38-41. https://doi.org/10.26634/jcir.6.4.14864

References

[1]. Balpande, V. V., Pande, A. B., Walke, M. J., Choudhari, B. D., Bagade, K. R. (2015). Design and Implementation of 16 Bit Processor on FPGA. International Journal of Advanced Research in Computer Science and Software Engineering, 5 (1),704-708.

[2]. Bhagat, S. M., & Bhandari, S. U. (2018). Design and Analysis of 16-bit RISC processor. Fourth International Conference on Computing, Communication, Control & Automation.

[3]. Jung, S. P., Xu, J., Lee, D., Park, J. S., Kim, K. J., & Cho, K. S. (2008, November). Design & verification of 16 bit RISC processor. In SoC Design Conference, 2008. ISOCC'08. International (Vol. 3, pp. 13-14). IEEE.

[4]. Parihar, R. K. S., & Reddy, S (2006). A report on Designing of 16-bit RISC Processor. Birla Institute of Technology and Science, Pilani.

[5]. Patil, A. S., & Shivaleelavathi, B. G. (2017). Design and implementation of pipelined 8-Bit RISC processor using Verilog HDL on FPGA. International Research Journal of Engineering and Technology (IRJET), 4(6), 1753-1756.

[6]. Sethulekshmi, R., Jazir, S., Rahiman, R. A., Karthik, R., & Abdulla, M. S. (2016, March). Verification of a RISC processor IP core using System Verilog. In Wireless Communications, Signal Processing and Networking (WiSPNET), International Conference on (pp. 1490-1493). IEEE.

[7]. Uma, R. (2012). Design and Performance analysis of 8 bit RISC Processor Using Xilinx Tool. International Journal of Engineering Research and Application, 2(2), 53-58.

If you have access to this article please login to view the article or kindly login to purchase the article

Single Article

	North Americas,UK, Middle East,Europe		India	Rest of world
	USD	EUR	INR	USD-ROW
Online	15	15

ADD TO CART

Options for accessing this content:

If you would like institutional access to this content, please recommend the title to your librarian.
If you already have i-manager's user account: Login above and proceed to purchase the article.
New Users: Please register, then proceed to purchase the article.