Analysis and Detection of Parametric Fault Detection for Analog Circuit Systems

R. Gurunadha*, K. Babulu**
*Assistant Professor, Department of Electronics and Communication Engineering, JNTUK-UCEV, Vizianagaram, Andhra Pradesh, India.
**Professor, Department of Electronics and Communication Engineering, JNTUK-UCEK, Kakinada, Andhra Pradesh, India.
Periodicity:July - December'2018
DOI : https://doi.org/10.26634/jes.7.1.14634

Abstract

A way to deal with simple fault analysis for circuits with resistance is exhibited dependent on measured fault identification calculation. The proposed model comprises of primer conclusion and choice principles in light of pre-decided values of the threshold. The analysis is performed on the circuit under test, and the relating reactions are acquired from various test focuses (components). The primery determination of result is obtained by utilizing an evidential calculation and fault area which is achieved dependent on the choice of control rules. The test result demonstrates that the proposed conclusion approach can deliver a more significant and precise determination and has the capacity to analyze disastrous and parametric faults in simple circuits with good and perfect precision.

Keywords

CUT: Circuit Under Test, SBT: simulation before test, SAT: simulation after testing.

How to Cite this Article?

Gurunadha,R., and Babulu,K.(2018) Analysis and Detection of Parametric Fault Detection for Analog Circuit Systems. i-manager's Journal on Embedded Systems,7(1),45-50. https://doi.org/10.26634/jes.7.1.14634

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